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| march 2015 docid13801 rev 21 1/155 1 AN2606 application note stm32 microcontroller system memory boot mode introduction the bootloader is stored in the internal boot rom memory (system memory) of stm32 devices. it is programmed by st during production. its main task is to download the application program to the internal flash me mory through one of the available serial peripherals (usart, can, usb, i 2 c, spi, etc.). a communication protocol is defined for each serial interface, with a compatible command set and sequences. this document applies to the products listed in table 1 . they are referred as stm32 throughout the document. the main features of the bootloader are the following: ? it uses an embedded serial interface to download the code with a predefined communication protocol ? it transfers and updates the flash memory c ode, the data, and the vector table sections this application note presents the general concept of the bootloader. it describes the supported peripherals and hardware requirements to be considered when using the bootloader of stm32 devices. however the sp ecifications of the lo w-level communication protocol for each supported serial peripheral are documented in separate documents. for specifications of the usart protocol used in the bootloader, refer to an3155. for the specification of the can protocol used in the bootloader, refer to an3154. for the specification of the dfu (usb device) protocol used in the bootloader, refer to an3156. for the specification of the i 2 c protocol used in the bootloader, refer to an4221. for the specification of the spi protocol used in the bootloader, refer to an4286. table 1. applicable products type part number or product series microcontrollers stm32l0 series: stm32l051xx, stm3 2l052xx, stm32l053xx, stm32l062xx, stm32l063xx stm32l1 series. stm32l4 series: stm32l476xx, stm32l486xx stm32f0 series: stm32f 03xxx, stm32f04 xxx, stm32f05xxx, stm32f07xxx stm32f1 series. stm32f2 series. stm32f3 series: stm32f301xx, stm32f 302xx, stm32f303xx, stm32f318xx, stm32f328xx, stm32f334xx, stm32f358xx, stm32f373xx, stm32f378xx stm32f4 series: stm32f401xx, stm32f 405xx, stm32f407xx, stm32f411xx, stm32f415xx, stm32f417xx, stm32f427xx, stm32f429xx, stm32f437xx, stm32f439xx, stm32f446xx www.st.com
contents AN2606 2/155 docid13801 rev 21 contents 1 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 general bootloader description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 bootloader activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 bootloader identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 hardware connection requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 bootloader memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 stm32f10xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 stm32f105xx/107xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.1 how to identify stm32f105xx/107xx bootloader versions . . . . . . . . . . 28 5.3.2 bootloade r unavailability on stm32f 105xx/stm32f107xx devices with a date code below 937 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.3 usart bootloader get-version command returns 0x20 instead of 0x22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.4 pa9 excessive power consumpt ion when usb cable is plugged in bootloader v2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 stm32f10xxx xl-density devices bootloader . . . . . . . . . . . . . . . . . . . 31 6.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 stm32l1xxx6(8/b) devices bootload er . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 docid13801 rev 21 3/155 AN2606 contents 7 7.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 stm32l1xxxc devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 stm32l1xxxd devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10 stm32f2xxxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1 bootloader v2.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2 bootloader v3.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11 stm32f40xxx/41xxx devices bootload er . . . . . . . . . . . . . . . . . . . . . . . 49 11.1 bootloader v3.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.1.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2 bootloader v9.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.2.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.2.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.2.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12 stm32f05xxx and stm32f030x8 devices bootloader . . . . . . . . . . . . . 59 12.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 contents AN2606 4/155 docid13801 rev 21 12.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13 stm32f03xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 14 stm32f373xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 15 stm32f302xb(c)/303xb(c) devices bootloader . . . . . . . . . . . . . . . . . . 66 15.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 15.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 15.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 16 stm32f378xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 16.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 16.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 16.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 17 stm32f358xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 17.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 17.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 17.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 18 stm32f42xxx/43xxx devices bootload er . . . . . . . . . . . . . . . . . . . . . . . 73 18.1 bootloader v7.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 18.1.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 18.1.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 18.1.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2 bootloader v9.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 18.2.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 docid13801 rev 21 5/155 AN2606 contents 7 19 stm32f04xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 19.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 19.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 19.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20 stm32f07xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 20.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 20.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 20.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 21 stm32f301xx/302x4(6/8) devices bootloader . . . . . . . . . . . . . . . . . . . 92 21.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 21.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 21.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 22 stm32f318xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 22.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 22.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 22.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 23 stm32f303x4(6/8)/334xx/328xx d evices bootloader . . . . . . . . . . . . . . 98 23.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 23.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 23.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 24 stm32f401xb(c) devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . 100 24.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 24.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 24.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 25 stm32f401xd(e) devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . 106 25.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 25.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 25.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 contents AN2606 6/155 docid13801 rev 21 26 stm32f411xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 26.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 26.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 26.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 27 stm32l1xxx6(8/b)a devices bootlo ader . . . . . . . . . . . . . . . . . . . . . . 118 27.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 27.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 27.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 28 stm32l1xxxe devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 28.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 28.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 28.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 29 stm32l05xxx/06xxx devices bootload er . . . . . . . . . . . . . . . . . . . . . . 124 29.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 29.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 29.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 30 stm32l476xx/486xx devices bootload er . . . . . . . . . . . . . . . . . . . . . . 127 30.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 30.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 30.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 31 stm32f446xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 31.1 bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 31.2 bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 31.3 bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 32 device-dependent bootloader parameters . . . . . . . . . . . . . . . . . . . . . 139 33 bootloader timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 33.1 bootloader startup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 33.2 usart connection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 docid13801 rev 21 7/155 AN2606 contents 7 33.3 usb connection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 33.4 i2c connection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 33.5 spi connection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 34 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 list of tables AN2606 8/155 docid13801 rev 21 list of tables table 1. applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. bootloader activation patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. embedded bootloaders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. stm32 f2 and f4 voltage range configuration us ing bootloader . . . . . . . . . . . . . . . . . . . 22 table 5. supported memory area by write, read, eras e and go commands. . . . . . . . . . . . . . . . . 22 table 6. stm32f10xxx configuration in system memory boo t mode . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. stm32f10xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. stm32f105xx/107xx configuration in system me mory boot mode . . . . . . . . . . . . . . . . . . 25 table 9. stm32f105xx/107xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. stm32f10xxx xl-density configuration in syst em memory boot mode . . . . . . . . . . . . . . 31 table 11. stm32f10xxx xl-density bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. stm32l1xxx6(8/b) configuration in system memo ry boot mode. . . . . . . . . . . . . . . . . . . . 33 table 13. stm32l1xxx6(8/b) bootloader versions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. stm32l1xxxc configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . 35 table 15. stm32l1xxxc bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 16. stm32l1xxxd configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . 38 table 17. stm32l1xxxd bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 18. stm32f2xxxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . . 42 table 19. stm32f2xxxx bootloader v2.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 20. stm32f2xxxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . . 45 table 21. stm32f2xxxx bootloader v3.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 22. stm32f40xxx/41xxx configuration in system memo ry boot mode . . . . . . . . . . . . . . . . . . 49 table 23. stm32f40xxx/41xxx bootloader v3.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 24. stm32f40xxx/41xxx configuration in system memo ry boot mode . . . . . . . . . . . . . . . . . . 53 table 25. stm32f40xxx/41xxx bootloader v9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 26. stm32f05xxx and stm32f030x8 devices configuration in system memory boot mode . 59 table 27. stm32f05xxx and stm32f030x8 devices bootloader versions . . . . . . . . . . . . . . . . . . . . 60 table 28. stm32f03xxx configuration in system memory boo t mode . . . . . . . . . . . . . . . . . . . . . . . 61 table 29. stm32f03xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 30. stm32f373xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . 63 table 31. stm32f373xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 32. stm32f302xb(c)/303xb(c) configuration in sy stem memory boot mode . . . . . . . . . . . . 66 table 33. stm32f302xb(c)/303xb(c) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 34. stm32f378xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . 69 table 35. stm32f378xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 36. stm32f358xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . 71 table 37. stm32f358xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 38. stm32f42xxx/43xxx configuration in system memo ry boot mode . . . . . . . . . . . . . . . . . . 73 table 39. stm32f42xxx/43xxx bootloader v7.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 40. stm32f42xxx/43xxx configuration in system memo ry boot mode . . . . . . . . . . . . . . . . . . 79 table 41. stm32f42xxx/43xxx bootloader v9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 42. stm32f04xxx configuration in system memory boo t mode . . . . . . . . . . . . . . . . . . . . . . . 86 table 43. stm32f04xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 44. stm32f07xxx configuration in system memory boo t mode . . . . . . . . . . . . . . . . . . . . . . . 89 table 45. stm32f07xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 46. stm32f301xx/302x4(6/8) configuration in system memory boot mode . . . . . . . . . . . . . . 92 table 47. stm32f301xx/302x4(6/8) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 48. stm32f318xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . 95 docid13801 rev 21 9/155 AN2606 list of tables 9 table 49. stm32f318xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 50. stm32f303x4(6/8)/334xx/328x x configuration in system memory boot mode . . . . . . . . . 98 table 51. stm32f303x4(6/8)/334xx/328xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 52. stm32f401xb(c) configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . 100 table 53. stm32f401xb(c) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 54. stm32f401xd(e) configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . 106 table 55. stm32f401xd(e) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 56. stm32f411xx configuration in system memory bo ot mode . . . . . . . . . . . . . . . . . . . . . . 112 table 57. stm32f411xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 58. stm32l1xxx6(8/b)a configuration in system me mory boot mode . . . . . . . . . . . . . . . . . 118 table 59. stm32l1xxx6(8/b)a bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 60. stm32l1xxxe configuration in system memory bo ot mode . . . . . . . . . . . . . . . . . . . . . . 120 table 61. stm32l1xxxe bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 62. stm32l05xxx/06xxx configuratio n in system memory boot mode . . . . . . . . . . . . . . . . . 124 table 63. stm32l05xxx/06xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 64. stm32l476xx/486xx configuration in system memo ry boot mode . . . . . . . . . . . . . . . . . 127 table 65. stm32l476xx/486xx bootloader v10.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 66. stm32f446xx configuration in system memory bo ot mode . . . . . . . . . . . . . . . . . . . . . . 133 table 67. stm32f446xx bootloader v9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 68. bootloader device-dependent parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 69. bootloader startup timings of stm32 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 70. usart bootloader minimum timings of stm32 device s . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 71. usb bootloader minimum timings of stm32 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 72. i2c bootloader minimum timings of stm32 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 73. spi bootloader minimum timings of stm32 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 74. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 list of figures AN2606 10/155 docid13801 rev 21 list of figures figure 1. usart connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 2. usb connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 3. i2c connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4. spi connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5. can connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6. bootloader for stm32f10xxx with usart1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. bootloader selection for stm32f105xx/107xx device s . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8. bootloader selection for stm32f10xxx xl-density devices. . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9. bootloader selection for stm32l1xxx6(8/b) devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 10. bootloader selection for stm32l1xxxc devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 11. bootloader selection for stm32l1xxxd devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 12. bootloader v2.x selection for stm32f2xxxx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 13. bootloader v3.x selection for stm32f2xxxx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 14. bootloader v3.x selection for stm32f40xxx/41xxx devices . . . . . . . . . . . . . . . . . . . . . . . 51 figure 15. bootloader v9.x selection fo r stm32f40xxx/41xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 16. bootloader selection for stm32f05xxx and st m32f030x8 devices . . . . . . . . . . . . . . . . . 60 figure 17. bootloader selection for stm32f03xxx devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 18. bootloader selection for stm32f373xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 19. bootloader selection for stm32f302xb(c)/303xb(c ) devices. . . . . . . . . . . . . . . . . . . . . . 68 figure 20. bootloader selection for stm32f378xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 21. bootloader selection for stm32f358xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 22. dual bank boot implemen tation for stm32f42xxx/43xxx bootloader v7.x . . . . . . . . . . . . 76 figure 23. bootloader v7.x selection fo r stm32f42xxx/43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 24. dual bank boot implemen tation for stm32f42xxx/43xxx bootloader v9.x . . . . . . . . . . . . 83 figure 25. bootloader v9.x selection fo r stm32f42xxx/43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 26. bootloader selection for stm32f04 xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 27. bootloader selection for stm32f07 xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 28. bootloader selection for stm32f301xx/302x4(6/8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 29. bootloader selection for stm32f318xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 30. bootloader selection for stm32f303x4(6/8)/334xx /328xx . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 31. bootloader selection for stm32f401xb(c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 32. bootloader selection for stm32f401xd(e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 33. bootloader selection for stm32f411xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 34. bootloader selection for stm32l1xxx6(8/b)a device s. . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 35. bootloader selection for stm32l1xxxe devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 36. bootloader selection for stm32l05xxx/06xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 37. dual bank boot implementation for stm32l 476xx/486xx bootloader v10.x . . . . . . . . . . 130 figure 38. bootloader v10.x selection for stm32l476xx/486xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 39. bootloader v9.x selection for stm32f446xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 40. bootloader startup timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 41. usart connection timing descript ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 42. usb connection timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 43. i2c connection timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 44. spi connection timing descript ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 docid13801 rev 21 11/155 AN2606 related documents 154 1 related documents for each supported product (listed in table 1 ), please refer to the following documents available from www.st.com : ? datasheet or databrief ? reference manual 2 glossary f0 series: stm32f05xxx and stm32f030x8 devices is used to refer to stm32f051x4, stm32f051x6, stm32f051x8, stm3 2f058x8 and stm32f030x8 devices. stm32f03xxx is used to refer to stm32f031x4, stm32f031x6, stm32f030f4, stm32f038x6 and stm32f030x6 devices. stm32f04xxx is used to refer to stm32f042x4 and stm32f042x6 devices. stm32f07xxx is used to refer to stm32f072x8 and stm32f072xb and stm32f071xb devices. f1 series: stm32f10xxx is used to refer to low-density, medium-density, high-density, low- density value line, medium-d ensity value line and high- density value line devices: low-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. medium-density devices are stm32f101xx, stm32f102xx and stm32f103xx microcontrollers where the flash memory density ranges between 64 and 128 kbytes. high-density devices are stm32f101xx and stm32f103xx microcontrollers where the flash memory density ra nges between 256 and 512 kbytes. low-density value line devices are stm32f100xx microcontrollers where the flash memory density ranges between 16 and 32 kbytes. medium-density value line devices are stm32f100xx microcontrollers where the flash memory density ranges between 64 and 128 kbytes. high-density value line devices are stm32f100xx microcontrollers where the flash memory density ranges between 256 and 5128 kbytes. stm32f105xx/107xx is used to refer to stm32f105xx and stm32f107xx devices. stm32f10xxx xl-density is used to refer to stm32f101xx and stm32f103xx devices where the flash memory density ranges between 768 kbytes and 1 mbyte. f2 series: stm32f2xxxx is used to refer to stm32f215xx, stm32f205xx, stm32f207xx and smt32f217xx devices. glossary AN2606 12/155 docid13801 rev 21 f3 series: stm32f373xx is used to refer to stm32f373x8, stm32f373xb and stm32f373xc devices. stm32f302xb(c)/303xb(c) is used to refer to stm32f302xb, stm32f302xc, stm32f303xb and stm32f303xc devices. stm32f378xx is used to refer to stm32f378xc devices. stm32f358xx is used to refer to stm32f358xc devices. stm32f301xx/302x4(6/8) is used to refer to stm32f301x4, stm32f301x6, stm32f301x8, stm32f302x4, stm3 2f302x6 and stm32f302x8 devices. stm32f318xx is used to refer to stm32f318xc devices. stm32f303x4(6/8)/334xx/328xx is used to refer to stm32f303x4, stm32f303x6, stm32f303x8, stm32f334x4, stm32f33 4x6, stm32f334x8, and stm32f328x8 devices. f4 series: stm32f40xxx/41xxx is used to refer to stm32f405xx, stm32f407xx, stm32f415xx and smt32f417xx devices. stm32f401xb(c) is used to refer to stm32f401xb and stm32f401xc devices. stm32f401xd(e) is used to refer to stm32f401xd and stm32f401xe devices. stm32f411xx is used to refer to stm32f411xd and stm32f411xe devices. stm32f42xxx/43xxx is used to refer to stm32f427xx, stm32f429xx, stm32f437xx and stm32f439xx devices stm32f446xx is used to refer to stm32f446xe and stm32f446xc devices l0 series: stm32l05xxx/06xxx is used to refer to stm32l051xx, stm32l052xx, stm32l053xx, stm32l062xx and stm3 2l063xx ultralow power devices. l1 series: stm32l1xxx6(8/b) is used to refer to stm32l1xxv6t6, stm32l1xxv6h6, stm32l1xxr6t6, stm32l1xxr6h6, stm32l1xxc6t6, stm32l1xxc6h6, stm32l1xxv8t6, stm32l1xxv8h6, stm32l1xxr8t6, stm32l1xxr8h6, stm32l1xxc8t6, stm32l1xxc8h6, stm32l1xxvbt6, stm32l1xxvbh6, stm32l1xxrbt6, stm32l1xxrbh6, st m32l1xxcbt6 and stm32l1xxcbh6 ultralow power devices. stm32l1xxx6(8/b)a is used to refer to stm32l1xxv6t6-a, stm32l1xxv6h6-a, stm32l1xxr6t6-a, stm32l1xxr6h6-a, stm32l1xxc6t6-a, stm32l1xxc6h6-a, stm32l1xxv8t6-a, stm32l1xxv8h6-a, stm32l1xxr8t6-a, stm32l1xxr8h6-a, stm32l1xxc8t6-a, stm32l1xxc8h6-a, stm32l1xxvbt6-a, st m32l1xxvbh6-a, stm32l1xxrbt6-a, stm32l1xxrbh6-a, stm32l1xxcbt6-a and stm32l1xxcbh6-a ultralow power devices. stm32l1xxxc is used to refer to stm32l1xxvct6, stm32l1xxvch6 , stm32l1xxrct6, stm32l1xxucy6, stm32l1xxcct6 and stm32l1xxccu6 ultralow power devices. stm32l1xxxd is used to refer to stm32l1xxzdt6, stm32l1xxqdh6, stm32l1xxvdt6, stm32l1xxrdy6, stm32l1xxrdt6, stm32l1xxzct6, docid13801 rev 21 13/155 AN2606 glossary 154 stm32l1xxqch6, stm32l1xxrcy6, stm32l1xxvct6-a and stm32l1xxrct6-a ultralow power devices. stm32l1xxxe is used to refer to stm32l1xxzet6, stm32l1xxqeh6, stm32l1xxvet6, stm32l1xxvey6 , and stm32l1xxret6 ul tralow power devices. l4 series: stm32l476xx/486xx is used to refer to stm32l476xe, stm32l476xg and stm32l486xg devices note: bl_usart_loop refers to the usart bootloader execution loop. bl_can_loop refers to the ca n bootloader execution loop. bl_i2c_loop refers to the i2c bootloader execution loop. bl_spi_loop refers to the spi bootloader execution loop. general bootloader description AN2606 14/155 docid13801 rev 21 3 general bootloader description 3.1 bootloader activation the bootloader is activated by applying one of these patterns: table 2. bootloader activation patterns note: the bootloader activation procedure is not the same for all stm32 products. in each stm32 product bootloader section we specify which pattern is used to execute bootloader. in addition to patterns described above, us er might execute bootloader by performing a jump to system memory from user code (refer to table 64 for system memory address). before jumping to bootloader user must: ? disable all peripheral clocks ? disable used pll ? disable interrupts ? clear pending interrupts system memory boot mode can be exited by getting out from bootloader activation condition and generating hardware reset or using go command to execute user code. note: for some products with dual bank mechanism, the jump to bootloader might result in jumping again to user code (and thus bootload er communication protoc ol is not executed). please refer to product's "dual bank boot implementation" flowchart for more details. i.e. in order to jump and execute bootloade r communication protocol, you might configure syscfg register by software to map system memory on a ddress 0x000000 00 prior to jumping, when this feature is available. patterns condition pattern1 boot0(pin) = 1 and boot1(pin) = 0 pattern2 boot0(pin) = 1 and nboot1(bit) = 1 pattern3 boot0 (pin)= 1, boot1(pin) = 0 and bfb2 (bit) = 1 boot0(pin) = 0, bfb2 (bit) = 0 and both banks don?t contain valid code boot0(pin) = 1, boot1(pin) = 0, bfb2 (bit) = 0 and both banks don?t contain valid code pattern4 boot0 (pin)= 1, boot1(pin) = 0 and bfb2 (bit) = 1 boot0(pin) = 0, bfb2 (bit) = 0 and both banks don?t contain valid code boot0(pin) = 1, boot1(pi n) = 0 and bfb2 (bit) = 0 pattern5 boot0 (pin)= 1, boot1(pin) = 0 and bfb2 (bit) = 0 boot0(pin) = 0, bfb2 (bit) = 1 and both banks don?t contain valid code boot0(pin) = 1, boot1(pi n) = 0 and bfb2 (bit) = 1 pattern6 boot0(pin) = 1, nboot1(bit) = 1 and nboot0_sw(bit) = 1 nboot0(bit) = 0, nboot1(bit) = 1 and nboot0_sw(bit) = 0 boot0(pin) = 0, nboot0_sw(bit) = 1 and main flash empty docid13801 rev 21 15/155 AN2606 general bootloader description 154 note: if you choose to execute the go command, t he peripheral registers used by the bootloader are not initialized to their default reset values before jumping to the user application. they should be reconfigured in the user application if they are used. so, if the iwdg is being used in the application, the iwdg prescaler value has to be adapted to meet the requirements of the application (since t he prescaler was set to its maximum value ). 3.2 bootloader identification depending on the stm32 device used, the bootloader may support one or more embedded serial peripherals used to download the code to the internal flash memory. the bootloader identifier (id) provides information abo ut the supported serial peripherals. for a given stm32 device, the bootloader is identified by means of the: 1. bootloader (protocol) version : version of the serial peripheral (usart, can, usb, etc.) communication protocol used in the bootloader. this version can be retrieved using the bootloader get version command. 2. bootloader identifier (id) : version of the stm32 device bootloader, coded on one byte in the 0xxy format , where: ? x specifies the embedded serial periphera l(s) used by the device bootloader: x = 1: one usart is used x = 2: two usarts are used x = 3: usart, can and dfu are used x = 4: usart and dfu are used x = 5: usart and i 2 c are used x = 6: i 2 c is used x = 7: usart, can, dfu and i 2 c are used x = 8: i 2 c and spi are used x = 9: usart, can, dfu, i 2 c and spi are used x = 10: usart, dfu and i 2 c are used x = 11: usart, i 2 c and spi are used x = 12: usart and spi are used x = 13: usart, dfu, i 2 c and spi are used ? y specifies the device bootloader version let us take the example of a bootloader id equal to 0x10. this means that it is the first version of the device bootl oader that uses only one usart. the bootloader id is programmed in the la st byte address - 1 of the device system memory and can be read by using the bootloader ?read memory? command or by direct access to the system memory via jtag/swd. the table below provides identification in formation about the bootloaders embedded in stm32 devices. general bootloader description AN2606 16/155 docid13801 rev 21 table 3. embedded bootloaders stm32 series device supported serial peripherals bootloader id bootloader (protocol) version id memory location f0 stm32f05xxx and stm32f030x8 devices usart1/usart2 0x21 0x1ffff7a6 usart (v3.1) stm32f03xxx usart1 0x10 0x1ffff7a6 usart (v3.1) stm32f04xxx usart1/usart2/ i2c1/ dfu (usb device fs) 0xa0 0x1ffff6a6 usart (v3.1) dfu (v2.2) i2c (v1.0) stm32f07xxx usart1/usart2/ i2c1/ dfu (usb device fs) 0xa1 0x1ffff6a6 usart (v3.1) dfu (v2.2) i2c (v1.0) f1 stm32f10xxx low-density usart1 na na usart (v2.2) medium-density usart1 na na usart (v2.2) high-density usart1 na na usart (v2.2) medium-density value line usart1 0x10 0x1ffff7d6 usart (v2.2) high-density value line usart1 0x10 0x1ffff7d6 usart (v2.2) stm32f105xx/107xx usart1 / usart2 (remapped) / can2 (remapped) / dfu (usb device) na na usart (v2.2 (1) ) can (v2.0) dfu(v2.2) stm32f10xxx xl-density usart1/usart2 (remapped) 0x21 0x1ffff7d6 usart (v3.0) f2 stm32f2xxxx usart1/usart3 0x20 0x1f ff77de usart (v3.0) usart1/usart3/ can2/ dfu (usb device fs) 0x33 0x1fff77de usart (v3.1) can (v2.0) dfu (v2.2) f3 stm32f373xx usart1/usart2/ dfu (usb device fs) 0x41 0x1ffff7a6 usart (v3.1) dfu (v2.2) stm32f378xx usart1/usart2/ i2c1 0x50 0x1ffff7a6 usart (v3.1) i2c (v1.0) stm32f302xb(c)/303xb(c) usart1/usart2/ dfu (usb device fs) 0x41 0x1ffff796 usart (v3.1) dfu (v2.2) stm32f358xx usart1/usart2/ i2c1 0x50 0x1ffff796 usart (v3.1) i2c (v1.0) stm32f301xx/302x4(6/8) usart1/usart2/ dfu (usb device fs) 0x40 0x1ffff796 usart (v3.1) dfu (v2.2) stm32f318xx usart1/usart2/ i2c1/ i2c3 0x50 0x1ffff796 usart (v3.1) i2c (v1.0) stm32f303x4(6/8)/334xx/328xx usart1/usart2/ i2c1 0x50 0x1ffff796 usart (v3.1) i2c (v1.0) docid13801 rev 21 17/155 AN2606 general bootloader description 154 f4 stm32f40xxx/41xxx usart1/usart3/ can2/ dfu (usb device fs) 0x31 0x1fff77de usart (v3.1) can (v2.0) dfu (v2.2) usart1/usart3/ can2 / dfu (usb device fs) /i2c1/i2c2/i2c3/spi1/ spi2 0x90 0x1fff77de usart (v3.1) can (v2.0) dfu (v2.2) spi(v1.1) i2c (v1.0) stm32f42xxx/43xxx usart1/usart3/ can2 /dfu (usb device fs) / i2c1/i2c2/i2c3 0x70 0x1fff76de usart (v3.1) can (v2.0) dfu (v2.2) i2c (v1.0) usart1/usart3/ can2 / dfu (usb device fs) / i2c1/i2c2/i2c3/spi1/ spi2/ spi4 0x90 0x1fff76de usart (v3.1) can (v2.0) dfu (v2.2) spi(v1.1) i2c (v1.0) stm32f401xb(c) usart1/usart2/ dfu (usb device fs)/ i2c1/i2c2/i2c3/ spi1/spi2/ spi3 0xd1 0x1fff76de usart (v3.1) dfu (v2.2) spi(v1.1) i2c (v1.0) stm32f401xd(e) usart1/usart2/ dfu (usb device fs)/ i2c1/i2c2/i2c3/ spi1/spi2/ spi3 0xd1 0x1fff76de usart (v3.1) dfu (v2.2) spi(v1.1) i2c (v1.1) stm32f411xx usart1/usart2/ dfu (usb device fs)/ i2c1/i2c2/i2c3/ spi1/spi2/ spi3 0xd0 0x1fff76de usart (v3.1) dfu (v2.2) spi(v1.1) i2c (v1.1) stm32f446xx usart1/usart3/ can2 / dfu (usb device fs) / i2c1/i2c2/i2c3/spi1/ spi2/ spi4 0x90 0x1fff76de usart (v3.1) can (v2.0) dfu (v2.2) spi(v1.1) i2c (v1.2) l0 stm32l05xxx/06xxx usart1/usart2/spi 1/ spi2 0xc0 0x1ff00ffe usart (v3.1) spi (v1.1) table 3. embedded bootloaders (continued) stm32 series device supported serial peripherals bootloader id bootloader (protocol) version id memory location general bootloader description AN2606 18/155 docid13801 rev 21 l1 stm32l1xxx6(8/b) usart1/usart2 0x20 0x1ff00ffe usart (v3.0) stm32l1xxx6(8/b)a usart1/usart2 0x20 0x1ff00ffe usart (v3.1) stm32l1xxxc usart1/usart2/ dfu (usb device fs) 0x40 0x1ff01ffe usart (v3.1) dfu (v2.2) stm32l1xxxd usart1/usart2/ dfu (usb device fs) 0x45 0x1ff01ffe usart (v3.1) dfu (v2.2) stm32l1xxxe usart1/usart2/ dfu (usb device fs) 0x40 0x1ff01ffe usart (v3.1) dfu (v2.2) l4 stm32l476xx/486xx usart1/usart2/ usart3/ i2c1/ i2c2/ i2c3/ dfu (usb device fs) 0xa3 0x1fff6ffe usart (v3.1) dfu (v2.2) i2c (v1.2) 1. for connectivity line devic es, the usart bootloader returns v2.0 instead of v2 .2 for the protocol version. for more details please refer to the ?stm32f105xx and stm32f107xx revision z? errata sheet available from http://www.st.com . table 3. embedded bootloaders (continued) stm32 series device supported serial peripherals bootloader id bootloader (protocol) version id memory location docid13801 rev 21 19/155 AN2606 general bootloader description 154 3.3 hardware connection requirements to use the usart bootloader, the host has to be connected to the (rx) and (tx) pins of the desired usartx interface via a serial cable. figure 1. usart connection 1. a pull-up resistor should be added, if pull- up resistor are not connected in host side. 2. an rs232 transceiver must be connected to adapt voltage level (3.3v - 12v) between stm32 device and host. note: +v typically 3.3 v and r value typically 1 00kohm.this value depend on the application and the used hardware. to use the dfu, connect the microcontroller's usb interface to a usb host (i.e. pc). figure 2. usb connection 1. this additional circuit permits to connect a pull-up resistor to (dp) pin using vbus when needed. refer to product section (table which describes stm32 configur ation in system memory boot mode) to know if an external pull-up resistor mu st be connected to (dp) pin. note: +v typically 3.3 v.this value depends on the application and the used hardware. h z d ,}?? ^ d d?? d]?}}v??}oo ? z y d y d y z y ' e ' e z ^??? d?v? ] ? = s z z ? 0 6 y 9 0 6 9 h ^ ,}?? ^ d d?? d]?}}v??}oo ? w d = s w d ' e ' e s ? x? < < ? < general bootloader description AN2606 20/155 docid13801 rev 21 to use the i2c bootloader, connect the host (m aster) and the desired i2cx interface (slave) together via the data (sda) and clock (scl) pins. a 1.8 kohm pull-up resistor has to be connected to both (sda) and (scl) lines. figure 3. i2c connection note: +v typically 3.3 v.this value depends on the application and the used hardware. to use the spi bootloader, conn ect the host (master) and the desired spix interface (slave) together via the (mos i), (miso) and (sck) pins. the (nss) pin must be connected to (gnd). a pull-down resistor should be connected to the (sck) line. figure 4. spi connection note: r value typically 10kohm. this value depe nds on the application and the used hardware. to use the can interface, the host has to be connected to the (rx) and (tx) pins of the desired canx interface via can transceiver and a serial cable. a 120 ohm resistor should be added as terminating resistor. 0 6 9 /? ,}?? ^ > ^ = s x? < x? < ^ > ^ ' e ' e ^ d d?? d]?}}v??}oo ? 0 6 9 ^ w / ,}?? ^ d d?? d]?}}v??}oo ? d k ^ / d / ^ k ' e e ^ ^ ^ < d k ^ / d / ^ k ' e ^ < z docid13801 rev 21 21/155 AN2606 general bootloader description 154 figure 5. can connection note: when a bootloader firmware supports dfu, it is mandatory that no usb host is connected to the usb peripheral during the selection phase of the other interfaces. after selection phase, the user can plug a u sb cable without impacting the selected bootloader execution except commands which generate a system reset. it is recommended to keep the rx pins of unused bootloader interfaces (usart_rx, spi_mosi, can_rx and usb d+/d- lines if presen t) at a known (low or high) level at the startup of the bootloader (detection phase). leav ing these pins floating during the detection phase might lead to activating unused interface. 3.4 bootloader memory management all write operations using bootloader command s must only be word-aligned (the address should be a multiple of 4). the number of data to be written must also be a multiple of 4 bytes (non-aligned half page write addresses are accepted). some products embed a bootloader that has some specific features: ? some products don?t support mass erase operation. to perform a mass erase operation using bootloader, two options are available: ? erase all sectors one by one using the erase command ? set protection level to level 1. then, set it to level 0 (using the read protect command and then the read unprotect command). this operation results in a mass erase of the internal flash memory. ? bootloader firmware of stm32 l1 and l0 series supports data memory in addition to standard memories (internal flash, internal sram, option bytes and system memory). the start address and the size of this area depend on the product, please refer to product reference manual for more information. data memory can be read and written but cannot be erased using the erase command. when writing in a data memory location, the bootloader firmware manages the erase operation of this location before any write. a write to data me mory must be word-aligned (address to be written should be a multiple of 4) and the number of data must also be a multiple of 4. to erase a data memory location, you can wr ite zeros at this location. ? bootloader firmware of stm32 f2, f4 and l4 series supports otp memory in addition to standard memories (internal flash, internal sram, option bytes and system memory). the start address and the size of this area depend on the product, please refer to product reference manual for more information. otp memory can be read and written but cannot be erased using erase command. when writing in an otp memory 0 6 9 e ,}?? ^ d d?? d]?}}v??}oo ? z y d y d y z y ' e ' e e d?v? ] ? e d?v? ] ? ez , ez > ? ? general bootloader description AN2606 22/155 docid13801 rev 21 location, make sure that the relative protection bit (in the last 16 bytes of the otp memory) is not reset. ? for stm32 f2 and f4 series the internal flash write oper ation format depends on the voltage range. by default write operation ar e allowed by one byte format (half-word, word and double-word operations are not allowed). to increase the speed of write operation, the user should apply the adequate voltage range that allows write operation by half-word, word or double-word and upda te this configuration on the fly by the bootloader software through a virtual memory location. this memory location is not physical but can be read and written usin g usual bootloader read/write operations according to the protocol in use. this memory location contains 4 bytes which are described in table below. it can be accessed by 1, 2, 3 or 4 bytes. however, reserved bytes should remain at thei r default values (0xff), ot herwise the request will be nacked. table 4. stm32 f2 and f4 voltage range configuration using bootloader the table below lists the valid memory area depending on the bootloader commands. address size description 0xffff0000 1 byte this byte controls the current value of the voltage range. 0x00: voltage range [1.8 v, 2.1 v] 0x01: voltage range [2.1 v, 2.4 v] 0x02: voltage range [2.4 v, 2.7 v] 0x03: voltage range [2.7 v, 3.6 v] 0x04: voltage range [2.7 v, 3.6 v] and double word write/erase operation is used. in this case it is mandatory to supply 9 v through the vpp pin (refer to the product reference manual for more details about the double-word write procedure). other: all other values are not supported and will be nacked. 0xffff0001 1 byte reserved. 0xff: default value. other: all other values are not supported and will be nacked. 0xffff0002 1 byte reserved. 0xff: default value. other: all other values are not supported and will be nacked. 0xffff0003 1 byte reserved. 0xff: default value. other: all other values are not supported and will be nacked. table 5. supported memory area by write, read, erase and go commands memory area write command read command erase command go command flash supported supported supported supported ram supported supported not supported supported system memory not supported supported not supported not supported data memory supported supported not supported not supported otp memory supported supported not supported not supported docid13801 rev 21 23/155 AN2606 stm32f10xxx devices bootloader 154 4 stm32f10xxx devices bootloader 4.1 bootloader configuration the stm32f10xxx bootloader is activated by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. table 6. stm32f10xxx configuration in system memory boot mode bootloader feature/peripheral state comment usart1 bootloader rcc hsi enabled the system clock frequency is 24 mhz using the pll. ram - 512 bytes starting from address 0x20000000 are used by the bootloader firmware. system memory - 2 kbytes starting from address 0x1ffff000 contain the bootloader firmware. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output push-pull pa9 pin: usart1 in transmission mode systick timer enabled used to automatically detect the serial baud rate from the host. stm32f10xxx devices bootloader AN2606 24/155 docid13801 rev 21 4.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 6. bootloader for stm32f10xxx with usart1 4.3 bootloader version the following table lists the stm32f10xxx devices bootloader versions: 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ 1 r ' l v d e o h d o o l q w h u u x s w v r x u f h v < h v table 7. stm32f10xxx bootloader versions bootloader version number description v2.0 initial bootloader version v2.1 ? updated go command to initialize the main stack pointer ? updated go command to return nack when jump address is in the option byte area or system memory area ? updated get id command to retu rn the device id on two bytes ? update the bootloader version to v2.1 v2.2 ? updated read memory, write memory and go commands to deny access with a nack response to the first 0x200 bytes of ram memory used by the bootloader ? updated readout unprotect command to initialize the whole ram content to 0x0 before rop disable operation docid13801 rev 21 25/155 AN2606 stm32f105xx/107xx devices bootloader 154 5 stm32f105xx/107xx devices bootloader 5.1 bootloader configuration the stm32f105xx/107xx bootloader is activated by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows the hardware resources used by this bootloader. table 8. stm32f105xx/107xx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 24 mhz using the pll. this is used only for usart1 and usart2 bootloaders and during can2, usb detection for can and dfu bootloaders (once can or dfu bootloader is selected, the clock source will be derived from the external crystal). hse enabled the external clock is mandatory only for dfu and can bootloaders and it must provide one of the following frequencies: 8 mhz, 14.7456 mhz or 25 mhz. for can bootloader, the pll is used only to generate 48 mhz when 14.7456 mhz is used as hse. for dfu bootloader, the pll is used to generate a 48 mhz system clock from all supported external clock frequencies. - the clock security system (css) interrupt is enabled for the can and dfu bootloaders. any failure (or removal) of the external clock will generate system reset. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). system memory - 18 kbytes starting from address 0x1fff b000 contain the bootloader firmware. ram - 4 kbytes starting from address 0x20000000 are used by the bootloader firmware. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output push-pull pa9 pin: usart1 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloader. stm32f105xx/107xx devices bootloader AN2606 26/155 docid13801 rev 21 the system clock is derived from the embedded internal high-speed rc for usartx bootloader. this internal clock is used also for dfu and can bootloaders but only for the selection phase. an external clock (8 mhz, 14.7456 mhz or 25 mhz.) is required for dfu and can bootloader execution after the selection phase. usart2 bootloader usart2 enabled once initialized, the usart2 configuration is: 8 bits, even parity and 1 stop bit. the usart2 uses its remapped pins. usart2_rx pin input pd6 pin: usart2 receive (remapped pin) usart2_tx pin output push-pull pd5 pin: usart2 transmit (remapped pin) can2 bootloader can2 enabled once initialized, the ca n2 configuration is: baudrate 125 kbps, 11-bit identifier. note: can1 is clocked during the can bootloader execution because can1 manages the communication between can2 and sram. can2_rx pin input pb5 pin: can2 receives (remapped pin). can2_tx pin output push-pull pb6 pin: can2 transmits (remapped pin). dfu bootloader usb enabled usb otg fs configured in forced device mode usb_vbus pin input pa9: power supply voltage line usb_dm pin input/output pa11 pin: usb_dm line usb_dp pin pa12 pin: usb_dp line. no external pull-up resistor is required table 8. stm32f105xx/107xx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 27/155 AN2606 stm32f105xx/107xx devices bootloader 154 5.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 7. bootloader selection for stm32f105xx/107xx devices 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n , ^ a ? d ,u exe? d , }? ?? d , [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v q r q r < h v < h v ' l v d e o h d o o l q w h u u x s w v r x u f h v < h v 8 6 % f d e o h ' h w h f w h g & r q i l j x u h 8 6 % ) u d p h g h w h f w h g r q & $ 1 [ v} + 6 ( 0 + ] 0 + ] r u 0 + ] ( [ h f x w h % / b & $ 1 b / r r s i r u & $ 1 [ * h q h u d w h 6 \ v w h p u h v h w v} ? ? & r q i l j x u h & $ 1 v} ' l v d e o h d o o l q w h u u x s w v r x u f h v 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] ? ? stm32f105xx/107xx devices bootloader AN2606 28/155 docid13801 rev 21 5.3 bootloader version the following table lists the stm32f105xx/107xx devices bootloader versions: table 9. stm32f105xx/107xx bootloader versions 5.3.1 how to identify stm 32f105xx/107xx bootloader versions bootloader v1.0 is implemented on devices which date code is below 937 (refer to stm32f105xx and stm32f107xx datasheet for where to find the date code on the device marking). bootloader v2.0 and v2.1 are implemented on devices with a date code higher or equal to 937. there are two ways to distinguish between bootloader versions: ? when using the usart bootloader, the get-version command defined in AN2606 and an3155 has been corrected in v2.1 version. it returns 0x22 instead of 0x20 as in bootloader v2.0. bootloader version number description v1.0 initial bootloader version v2.0 ? bootloader detection mechanism updat ed to fix the issue when gpios of unused peripherals in this bootloader are connected to low level or left floating during the detection phase. for more details please refer to section 5.3.2 . ? vector table set to 0x1fff b000 instead of 0x0000 0000 ? go command updated (for all bootloaders): usart1, usart2, can2, gpioa, gpiob, gpiod and systick peri pheral registers are set to their default reset values ? dfu bootloader: usb pending interrupt cleared before executing the leave dfu command ? dfu subprotocol version changed from v1.0 to v1.2 ? bootloader version updated to v2.0 v2.1 ? fixed pa9 excessive consumption described in section 5.3.4 . ? get-version command (defined in an3155) corrected. it returns 0x22 instead of 0x20 in bootloader v2.0. refer to section 5.3.3 for more details. ? bootloader version updated to v2.1 v2.2 ? fixed dfu option bytes descriptor (set to ?e? instead of ?g? because it is read/write and not erasable). ? fixed dfu polling timings for flash read/write/erase operations. ? robustness enhancements for dfu bootloader interface. ? updated bootloader version to v2.2. docid13801 rev 21 29/155 AN2606 stm32f105xx/107xx devices bootloader 154 ? the values of the vector table at the beginning of the bootloader code are different. the user software (or via jtag/swd) reads 0x1fffe945 at address 0x1fffb004 for bootloader v2.0 0x1fffe9a1 for bootloader v2.1, and 0x1fffe9c1 for bootloader v2.2. ? the dfu version is the following: ? v2.1 in bootloader v2.1 ? v2.2 in bootloader v2.2. it can be read through the bcddevice field of the dfu device descriptor. 5.3.2 bootloader unavailability on stm32f105xx/stm32f107xx devices with a date code below 937 description the bootloader cannot be used if the usar t1_rx (pa10), usart2_rx (pd6, remapped), can2_rx (pb5, remapped), otg_fs_dm (pa11), and/or otg_fs_dp (pa12) pin(s) are held low or left floating during the bootloader activation phase. the bootloader cannot be connected through can2 (remapped), dfu (otg fs in device mode), usart1 or usart2 (remapped). on 64-pin packages, the usart2_rx signal rem apped pd6 pin is not available and it is internally grounded. in this case, the bootloader cannot be used at all. workaround ? for 64-pin packages none. the bootloader cannot be used. ? for 100-pin packages depending on the used peripheral, the pins for the unused peripherals have to be kept at a high level during the bootloader activation phase as described below: ? if usart1 is used to connect to the bootloader, pd6 and pb5 have to be kept at a high level. ? if usart2 is used to connect to the bootloader, pa10, pb5, pa11 and pa12 have to be kept at a high level. ? if can2 is used to connect to the bootloader, pa10, pd6, pa11 and pa12 have to be kept at a high level. ? if dfu is used to connect to the bootloader, pa10, pb5 and pd6 have to be kept at a high level. note: this limitation applies only to stm32f105xx and stm32f107xx devices with a date code below 937. stm32f105xx and stm32f107xx devices with a date code higher or equal to 937 are not impacted. see stm32f105xx and stm32f107xx datasheets for where to find the date code on the device marking. stm32f105xx/107xx devices bootloader AN2606 30/155 docid13801 rev 21 5.3.3 usart bootloader get-version command returns 0x20 instead of 0x22 description in usart mode, the get-version command (defined in an3155) returns 0x20 instead of 0x20. this limitation is present on bootloader versions v1.0 and v2.0, while it is fixed in bootloader version 2.1. workaround none. 5.3.4 pa9 excessive power consumpt ion when usb cable is plugged in bootloader v2.0 description when connecting a usb cable after booting from system-memory mode, pa9 pin (connected to v bus =5 v) is also shared with usart tx pin which is configured as alternate push-pull and forced to 0 since the usart peri pheral is not yet clocked. as a consequence, a current higher than 25 ma is drained by pa9 i/o and ma y affect the i/o pad reliability. this limitation is fixed in bo otloader version 2.1 by configuring pa9 as alternate function push-pull when a correct 0x7f is received on rx pin and the usart is clocked. otherwise, pa9 is configured as alternate input floating. workaround none. docid13801 rev 21 31/155 AN2606 stm32f10xxx xl-density devices bootloader 154 6 stm32f10xxx xl-density devices bootloader 6.1 bootloader configuration the stm32f10xxx xl-density bootloader is activated by applying pattern3 (described in table 2: bootloader activation patterns ). the following table shows the hardware resources used by this bootloader: the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. table 10. stm32f10xxx xl-density configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 24 mhz using the pll. ram - 2 kbytes starting from address 0x2000 0000 are used by the bootloader firmware. system memory - 6 kbytes starting from address 0x1fff e000 contain the bootloader firmware. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output push-pull pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized, the usart2 configuration is: 8 bits, even parity and 1 stop bit. usart2_rx pin input pd6 pin: usart2 receives (remapped pins). usart2_tx pin output push-pull pd5 pin: usart2 transmits (remapped pins). usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host. stm32f10xxx xl-density devices bootloader AN2606 32/155 docid13801 rev 21 6.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 8. bootloader selection for stm32f10xxx xl-density devices 6.3 bootloader version the following table lists the stm32f10xxx xl-density devices bootloader versions: table 11. stm32f10xxx xl-density bootloader versions 0 6 9 6 \ v w h p 5 h v h w [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ q r < h v & ? ]? ? ? ? ~ & ? a /( so ???? ]? ]?z]v ]v?x ^ z d ? ?? /( so ??? ]? ]?z]v ]v?x ^ z d ? ?? 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n & r q w l q x h % r r w o r d g h u h [ h f x w l r q ? ? v} v} ' l v d e o h d o o l q w h u u x s w v r x u f h v v} - x p s w r x v h u f r g h l q % d q n :u? ?} ? ? } ]v vl ? ? ? ? bootloader version number description v2.1 initial bootloader version docid13801 rev 21 33/155 AN2606 stm32l1xxx6(8/b) devices bootloader 154 7 stm32l1xxx6(8/b) devices bootloader 7.1 bootloader configuration the stm32l1xxx6(8/b) bootloader is activated by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. table 12. stm32l1xxx6(8/b) configur ation in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 16 mhz. ram - 2 kbytes starting from address 0x20000000 are used by the bootloader firmware. system memory - 4 kbytes starting from address 0x1ff00000 contain the bootloader firmware. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - voltage range is set to voltage range 1. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized, the usart2 configuration is: 8 bits, even parity and 1 stop bit. usart2_rx pin input pd6 pin: usart2 in reception mode usart2_tx pin output pd5 pin: usart2 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host. stm32l1xxx6(8/b) devices bootloader AN2606 34/155 docid13801 rev 21 7.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 9. bootloader selection for stm32l1xxx6(8/b) devices 7.3 bootloader version the following table lists the stm32l1xxx6(8/b) devices bootloader versions: 0 6 9 6 \ v w h p 5 h v h w [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ q r < h v 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n ' l v d e o h d o o l q w h u u x s w v r x u f h v table 13. stm32l1xxx6(8/b) bootloader versions bootloader version number description known limitations v2.0 initial bootloader version when a read memory command or write memory command is issued with an unsupported memory address and a correct address checksum (ie. address 0x6000 0000), the command is aborted by the bootloader device, but the nack (0x1f) is not sent to the host. as a result, the next 2 bytes (which are the number of bytes to be read/written and its checksum) are considered as a new command and its checksum. (1) 1. if the ?number of data - 1? (n-1) to be read/written is not equal to a valid command code, then the limitation is not perceived from the host since the command is nacked anyway (as an unsupported new command). docid13801 rev 21 35/155 AN2606 stm32l1xxxc devices bootloader 154 8 stm32l1xxxc devices bootloader 8.1 bootloader configuration the stm32l1xxxc bootloader is activated by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 14. stm32l1xxxc configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 16 mhz using the hsi. this is used only for usart1 and usart2 bootloaders and during usb detection for dfu bootloader (once the dfu bootloader is selected, the clock source is derived from the external crystal). hse enabled the external clock is mandatory only for the dfu bootloader and must be in the following range: [24, 16, 12, 8, 6, 4, 3, 2] mhz. the pll is used to generate the usb 48 mhz clock and the 32 mhz clock for the system clock. - the clock security system (css) interrupt is enabled for the dfu bootloader. any failure (or removal) of the external clock generates a system reset. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog resets (in case the hardware iwdg option was previously enabled by the user). power voltage range is set to voltage range 1. system memory - 8 kbytes starting from address 0x1ff0 0000. this area contains the bootloader firmware. ram - 4 kbytes starting from address 0x20000000 are used by the bootloader firmware. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for the usartx bootloader. stm32l1xxxc devices bootloader AN2606 36/155 docid13801 rev 21 the system clock is derived from the embed ded internal high-speed rc for the usartx bootloader. this internal clock is also used the for dfu bootloader but only for the selection phase. an external clock in the range of [24, 16, 12, 8, 6, 4, 3, 2] mhz is required for the execution of the dfu bootloader after the selection phase. usart2 bootloader usart2 enabled once initialized, the usart2 configuration is 8 bits, even parity and 1 stop bit. the usart2 uses its remapped pins. usart2_rx pin input pd6 pin: usart2 in reception mode usart2_tx pin output pd5 pin: usart2 in transmission mode dfu bootloader usb enabled usb used in fs mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line an external pull-up resistor 1.5 kohm must be connected to usb_dp pin. table 14. stm32l1xxxc configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 37/155 AN2606 stm32l1xxxc devices bootloader 154 8.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 10. bootloader selection for stm32l1xxxc devices 8.3 bootloader version the following table lists the stm32l1xxxc devices bootloader versions: initial bootloader version for the usart interface, two consecutive nacks in stead of 1 nack are sent when a read memory or write memory command is sent and the rdp level is active. 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n + 6 ( 0 + ] [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 % & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v 1 r 1 r < h v < h v * h q h u d w h 6 \ v w h p u h v h w 1 r ' l v d e o h d o o l q w h u u x s w v r x u f h v < h v 8 6 % f d e o h ' h w h f w h g table 15. stm32l1xxxc bootloader versions bootloader version number description known limitations v4.0 stm32l1xxxd devices bootloader AN2606 38/155 docid13801 rev 21 9 stm32l1xxxd devices bootloader 9.1 bootloader configuration the stm32l1xxxd bootloader is activated by applying pattern4 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 16. stm32l1xxxd configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 16 mhz using the hsi. this is used only for usart1 and usart2 bootloaders and during usb detection for dfu bootloader (once the dfu bootloader is selected, the clock source will be derived from the external crystal). hse enabled the external clock is mandatory only for dfu bootloader and it must be in the following range: [24, 16, 12, 8, 6, 4, 3, 2] mhz. the pll is used to generate the usb 48 mhz clock and the 32 mhz clock for the system clock. - the clock security system (css) interrupt is enabled for the dfu bootloader. any failure (or removal) of the external clock generates system reset. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - voltage range is set to voltage range 1. system memory - 8 kbytes starting from address 0x1ff0 0000. this area contains the bootloader firmware. ram - 4 kbytes starting from address 0x20000000 are used by the bootloader firmware. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloader. docid13801 rev 21 39/155 AN2606 stm32l1xxxd devices bootloader 154 the system clock is derived from the embedded internal high-speed rc for usartx bootloader. this internal clock is used also for dfu bootloader but only for the selection phase. an external clock in the range of [24, 16, 12, 8, 6, 4, 3, 2] mhz is required for dfu bootloader execution after the selection phase. usart2 bootloader usart2 enabled once initialized, the usart2 configuration is: 8 bits, even parity and 1 stop bit. the usart2 uses its remapped pins. usart2_rx pin input pd6 pin: usart2 in reception mode usart2_tx pin output pd5 pin: usart2 in transmission mode dfu bootloader usb enabled usb used in fs mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line an external pull-up re sistor 1.5 kohm must be connected to usb_dp pin. table 16. stm32l1xxxd configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32l1xxxd devices bootloader AN2606 40/155 docid13801 rev 21 9.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 11. bootloader selection for stm32l1xxxd devices 0 6 9 6 \ v w h p 5 h v h w & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ q r q r & ? ]? ? ? ? ~ & ? a /( so ???? ]? ]?z]v ]v?x ^ z d ? ?? /( so ??? ]? ]?z]v ]v?x ^ z d ? ?? 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n & r q w l q x h % r r w o r d g h u h [ h f x w l r q v} ? ? v} v} ' l v d e o h d o o l q w h u u x s w v r x u f h v v} - x p s w r x v h u f r g h l q % d q n :u? ?} ? ? } ]v vl ? ? ? ? /( so ???? ]? ]?z]v ]v?x ^ z d ? ?? /( so ??? ]? ]?z]v ]v?x ^ z d ? ?? v} v} - x p s w r x v h u f r g h l q % d q n :u? ?} ? ? } ]v vl ? ? ? ? w?}? ?]}v o o? vo ? ? w h o}l ~zo? 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v < h v + 6 ( g h w h f w h g ? ? * h q h u d w h 6 \ v w h p u h v h w v} & r q i l j x u h 8 6 % [ ) u h f h l y h g r q 8 6 $ 5 7 [ 8 6 % f d e o h ' h w h f w h g < h v docid13801 rev 21 41/155 AN2606 stm32l1xxxd devices bootloader 154 9.3 bootloader version the following table lists the stm32l1xxxd devices bootloader versions: table 17. stm32l1xxxd bootloader versions bootloader version number description known limitations v4.1 initial bootloader version ? in the bootloader code the pa13 (jtms/swdio) i/o output speed is configured to 400 khz, as consequence some debugger can not connect to the device in serial wire mode when the bootloader is running. ? when the dfu bootloader is selected, the rtc is reset and thus all rtc information (calendar, alarm, ...) will be lost including backup registers. note: when the usart bootloader is selected there is no change on the rtc configuration (including backup registers). v4.2 fix v4.1 limitations (available on rev.z devices only.) ? stack overflow by 8 bytes when jumping to bank1/bank2 if bfb2=0 or when read protection level is set to 2. workaround: the user code should force in the startup file the top of stack address before to jump to the main program. this can be done in the ?reset_handler? routine. ? when the stack of the user code is placed outside the sram (ie. @ 0x2000c000) the bootloader cannot jump to that user code which is considered invalid. this might happen when using compilers which place the stack at a non-physical address at the top of the sram (ie. @ 0x2000c000). workaround: place manually the stack at a physical address. v4.5 fix v4.2 limitations. dfu interface robustness enhancements (available on rev.y devices only). ? for the usart interface, two consecutive nacks (instead of 1 nack) are sent when a read memory or write memory command is sent and the rdp level is active. stm32f2xxxx devices bootloader AN2606 42/155 docid13801 rev 21 10 stm32f2xxxx devices bootloader two bootloader versions are available on stm32f2xxxx devices: ? v2.0 supporting usart1 and usart3 this version is embedded in stm32f2xxxx devices revision b. ? v3.2 supporting usart1, usart3 , can2 and dfu (usb fs device) this version is embedded in stm32f2xxxx devices revision x and y. 10.1 bootloader v2.x 10.1.1 bootloader configuration the stm32f2xxxx bootloader is activated by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 18. stm32f2xxxx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 24 mhz. ram - 8 kbytes starting from address 0x2000 0000. system memory - 30688 bytes starting from address 0x1fff 0000 contain the bootloader firmware. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - voltage range is set to [1.62 v, 2.1 v]. in this range internal flash write operations are allowed only in byte format (half-word, word and double-word operations are not allowed). the voltage range can be configured in run time using bootloader commands. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart3 bootloader (on pc10/pc11) usart3 enabled once initialized, the usart3 configuration is: 8 bits, even parity and 1 stop bit. usart3_rx pin input pc11 pin: usart3 in reception mode usart3_tx pin output pc10 pin: usart3 in transmission mode docid13801 rev 21 43/155 AN2606 stm32f2xxxx devices bootloader 154 the system clock is derived from the embedded internal high-speed rc. no external quartz is required for the bootloader code. 10.1.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 12. bootloader v2.x selection for stm32f2xxxx devices usart3 bootloader (on pb10/pb11) usart3 enabled once initialized, the usart3 configuration is: 8 bits, even parity and 1 stop bit usart3_rx pin input pb11 pin: usart3 in reception mode usart3_tx pin output pb10 pin: usart3 in transmission mode usart1 and usart3 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host. table 18. stm32f2xxxx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v q r stm32f2xxxx devices bootloader AN2606 44/155 docid13801 rev 21 10.1.3 bootloader version this following table lists the stm32f2xxxx devices v2.x bootloader versions: table 19. stm32f2xxxx bootloader v2.x versions bootloader version number description known limitations v2.0 initial v2.x bootloader version when a read memory command or write memory command is issued with an unsupported memory address and a correct address checksum (ie. address 0x6000 0000), the command is aborted by the bootloader device, but the nack (0x1f) is not sent to the host. as a result, the next 2 bytes (which are the number of bytes to be read/written and its checksum) are considered as a new command and its checksum. for the can interface, the write unprotect command is not functional. instead you can use write memory command and write directly to the option bytes in order to disable the write protection. (1) 1. if the ?number of data - 1? (n-1) to be read/written is not equal to a valid command code (0x00, 0x01, 0x02, 0x11, 0x21, 0x31, 0x43, 0x44, 0x63, 0x73, 0x82 or 0x92) , then the limitation is not perceived from the host since the command is nacked anyway (as an unsupported new command). docid13801 rev 21 45/155 AN2606 stm32f2xxxx devices bootloader 154 10.2 bootloader v3.x 10.2.1 bootloader configuration the stm32f2xxxx bootloader is activated by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 20. stm32f2xxxx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 24 mhz using the pll. the hsi clock source is used at startup (interface detection phase) and when usartx interfaces are selected (once can or dfu bootloader is selected, the clock source will be derived from the external crystal). hse enabled the system clock frequency is 60 mhz. the hse clock source is used only when the can or the dfu (usb fs device) interfaces are selected. the external clock must provide a frequency multiple of 1 mhz and ranging from 4 mhz to 26 mhz. - the clock security system (css) interrupt is enabled for the can and dfu bootloaders. any failure (or removal) of the external clock generates system reset. ram - 8 kbytes starting from address 0x20000000 are used by the bootloader firmware. system memory - 30688 bytes starting from address 0x1ff0 0000 contain the bootloader firmware. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - voltage range is set to [1.62 v, 2.1 v]. in this range internal flash write operations are allowed only in byte format (half-word, word and double-word operations are not allowed). the voltage range can be configured in run time using bootloader commands. stm32f2xxxx devices bootloader AN2606 46/155 docid13801 rev 21 the system clock is derived from the embedded internal high-speed rc for usartx bootloaders. this internal clock is also used for can and dfu (usb fs device) but only for the selection phase. an exte rnal clock multiple of 1 mhz (between 4 and 26 mhz) is required for can and dfu bootloader execution after the selection phase. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart3 bootloader (on pb10/pb11) usart3 enabled once initialized, the usart3 configuration is: 8 bits, even parity and 1 stop bit. usart3_rx pin input pb11 pin: usart3 in reception mode usart3_tx pin output pb10 pin: usart3 in transmission mode usart3 bootloader (on pc10/pc11) usart3 enabled once initialized, the usart3 configuration is: 8 bits, even parity and 1 stop bit. usart3_rx pin input pc11 pin: usart3 in reception mode usart3_tx pin output pc10 pin: usart3 in transmission mode usart1 and usart3 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. can2 bootloader can2 enabled once initialized, the can2 configuration is: baudrate 125 kbps, 11-bit identifier. note: can1 is clocked during can2 bootloader execution because can1 manages the communication between can2 and sram. can2_rx pin input pb5 pin: can2 in reception mode can2_tx pin output pb13 pin: can2 in transmission mode dfu bootloader usb enabled usb otg fs configured in forced device mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line no external pull-up resistor is required can2 and dfu bootloaders tim11 enabled this timer is used to determine the value of the hse. once the hse frequency is determined, the system clock is configured to 60 mhz using pll and hse. table 20. stm32f2xxxx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 47/155 AN2606 stm32f2xxxx devices bootloader 154 10.2.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 13. bootloader v3.x selection for stm32f2xxxx devices 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v < h v * h q h u d w h 6 \ v w h p u h v h w & r q i l j x u h 8 6 % 2 7 * ) 6 g h y l f h ) u d p h g h w h f w h g r q & $ 1 [ s l q q r + 6 ( g h w h f w h g ( [ h f x w h % / b & $ 1 b / r r s i r u & $ 1 [ 8 6 % f d e o h ' h w h f w h g [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v q r q r & r q i l j x u h & $ 1 + 6 ( g h w h f w h g ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v \ h v \ h v q r q r 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] stm32f2xxxx devices bootloader AN2606 48/155 docid13801 rev 21 10.2.3 bootloader version the following table lists the stm32f2xxxx devices v3.x b ootloader versions: table 21. stm32f2xxxx bootloader v3.x versions bootloader version number description known limitations v3.2 initial v3.x bootloader version. ? when a read memory command or write memory command is issued with an unsupported memory address and a correct address checksum (ie. address 0x6000 0000), the command is aborted by the bootloader device, but the nack (0x1f) is not sent to the host. as a result, the next 2 bytes (which are the number of bytes to be read/writt en and its checksum) are considered as a new command and its checksum (1) . ? option bytes, otp and device feature descriptors (in dfu interface) are set to ?g? instead of ?e? (not erasable memory areas). 1. if the ?number of data - 1? (n-1) to be read/written is not equal to a valid command code (0x00, 0x01, 0x02, 0x11, 0x21, 0x31, 0x43, 0x44, 0x63, 0x73, 0x82 or 0x92) , then the limitation is not perceived from the host since the command is nacked anyway (as an unsupported new command). v3.3 fix v3.2 limitations. dfu interface robustness enhancement. ? for the usart interface, two consecutive nacks (instead of 1 nack) are sent when a read memory or write memory command is sent and the rdp level is active. ? for the can interface, the write unprotect command is not functional. instead you can use write memory command and write directly to the option bytes in order to disable the write protection. docid13801 rev 21 49/155 AN2606 stm32f40xxx/41xxx devices bootloader 154 11 stm32f40xxx/41xxx devices bootloader 11.1 bootloader v3.x 11.1.1 bootloader configuration the stm32f40xxx/41xxx bootloader is activa ted by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 22. stm32f40xxx/41xxx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 24 mhz using the pll. the hsi clock source is used at startup (interface detection phase) and when usartx interfaces are selected (once can or dfu bootloader is selected, the clock source will be derived from the external crystal). hse enabled the system clock frequency is 60 mhz. the hse clock source is used only when the can or the dfu (usb fs device) interfaces are selected. the external clock must provide a frequency multiple of 1 mhz and ranging from 4 mhz to 26 mhz. - the clock security system (css) interrupt is enabled for the can and dfu bootloaders. any failure (or removal) of the external clock generates system reset. ram - 8 kbytes starting from address 0x20000000 are used by the bootloader firmware. system memory - 30688 bytes starting from address 0x1fff 0000 contain the bootloader firmware. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - voltage range is set to [1.62 v, 2.1 v]. in this range internal flash write operations are allowed only in byte format (half-word, word and double-word operations are not allowed). the voltage range can be configured in run time using bootloader commands. stm32f40xxx/41xxx devices bootloader AN2606 50/155 docid13801 rev 21 the system clock is derived from the embedded internal high-speed rc for usartx bootloaders. this internal clock is also used for can and dfu (usb fs device) but only for the selection phase. an exte rnal clock multiple of 1 mhz (between 4 and 26 mhz) is required for can and dfu bootloader execution after the selection phase. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart3 bootloader (on pb10/pb11) usart3 enabled once initialized, the usart3 configuration is: 8 bits, even parity and 1 stop bit. usart3_rx pin input pb11 pin: usart3 in reception mode usart3_tx pin output pb10 pin: usart3 in transmission mode usart3 bootloader (on pc10/pc11) usart3 enabled once initialized, the usart3 configuration is: 8 bits, even parity and 1 stop bit. usart3_rx pin input pc11 pin: usart3 in reception mode usart3_tx pin output pc10 pin: usart3 in transmission mode usart1 and usart3 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. can2 bootloader can2 enabled once initialized, the can2 configuration is: baudrate 125 kbps, 11-bit identifier. note: can1 is clocked during can2 bootloader execution because can1 manages the communication between can2 and sram. can2_rx pin input pb5 pin: can2 in reception mode can2_tx pin output pb13 pin: can2 in transmission mode dfu bootloader usb enabled usb otg fs configured in forced device mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line no external pull-up resistor is required can2 and dfu bootloaders tim11 enabled this timer is used to determine the value of the hse. once the hse frequency is determined, the system clock is configured to 60 mhz using pll and hse. table 22. stm32f40xxx/41xxx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 51/155 AN2606 stm32f40xxx/41xxx devices bootloader 154 11.1.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 14. bootloader v3.x selection for stm32f40xxx/41xxx devices 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v < h v * h q h u d w h 6 \ v w h p u h v h w & r q i l j x u h 8 6 % 2 7 * ) 6 g h y l f h ) u d p h g h w h f w h g r q & $ 1 [ s l q q r + 6 ( g h w h f w h g ( [ h f x w h % / b & $ 1 b / r r s i r u & $ 1 [ 8 6 % f d e o h ' h w h f w h g [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v q r q r & r q i l j x u h & $ 1 + 6 ( g h w h f w h g ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v \ h v \ h v q r q r 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] stm32f40xxx/41xxx devices bootloader AN2606 52/155 docid13801 rev 21 11.1.3 bootloader version the following table lists the stm32f40xxx/ 41xxx devices v3.x bootloader versions: table 23. stm32f40xxx/41xxx bootloader v3.x versions bootloader version number description known limitations v3.0 initial bootloader version ? when a read memory command or write memory command is issued with an unsupported memory address and a correct address checksum (ie. address 0x6000 0000), the command is aborted by the bootloader device, but the nack (0x1f) is not sent to the host. as a result, the next 2 bytes (which are the number of bytes to be read/writt en and its checksum) are considered as a new command and its checksum (1) . ? option bytes, otp and device feature descriptors (in dfu interface) are set to ?g? instead of ?e? (not erasable memory areas). 1. if the ?number of data - 1? (n-1) to be read/written is not equal to a valid command code (0x00, 0x01, 0x02, 0x11, 0x21, 0x31, 0x43, 0x44, 0x63, 0x73, 0x82 or 0x92) , then the limitation is not perceived from the host since the command is nacked anyway (as an unsupported new command). v3.1 fix v3.0 limitations. dfu interface robustness enhancement. ? for the usart interface, two consecutive nacks (instead of 1 nack) are sent when a read memory or write memory command is sent and the rdp level is active. ? for the can interface, the write unprotect command is not functional. instead you can use write memory command and write directly to the option bytes in order to disable the write protection. docid13801 rev 21 53/155 AN2606 stm32f40xxx/41xxx devices bootloader 154 11.2 bootloader v9.x 11.2.1 bootloader configuration the stm32f40xxx/41xxx bootloader is activa ted by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 24. stm32f40xxx/41xxx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 60 mhz using the pll. the hsi clock source is used at startup (interface detection phase) and when usart or spi or i2c interfaces are selected (once can or dfu bootloader is selected, the clock source will be derived from the external crystal). hse enabled the system clock frequency is 60 mhz. the hse clock source is used only when the can or the dfu (usb fs device) interfaces are selected. the external clock must provide a frequency multiple of 1 mhz and ranging from 4 mhz to 26 mhz. - the clock security system (css) interrupt is enabled for the can and dfu bootloaders. any failure (or removal) of the external clock generates system reset. ram - 12 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 30424 bytes starting from address 0x1fff0000, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - voltage range is set to [1.62 v, 2.1 v]. in this range internal flash write operations are allowed only in byte format (half-word, word and double-word operations are not allowed). the voltage range can be configured in run time using bootloader commands. stm32f40xxx/41xxx devices bootloader AN2606 54/155 docid13801 rev 21 usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart3 bootloader (on pb10/pb11) usart3 enabled once initialized the usart3 configuration is: 8-bits, even parity and 1 stop bit usart3_rx pin input pb11 pin: usart3 in reception mode usart3_tx pin output pb10 pin: usart3 in transmission mode usart3 bootloader (on pc10/pc11) usart3 enabled once initialized the usart3 configuration is: 8-bits, even parity and 1 stop bit usart3_rx pin input pc11 pin: usart3 in reception mode usart3_tx pin output pc10 pin: usart3 in transmission mode usart1 and usart3 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. can2 bootloader can2 enabled once initialized the can2 configuration is: baudrate 125 kbps, 11-bit identifier. note: can1 is clocked during can2 bootloader execution because can1 manages the communication between can2 and sram. can2_rx pin input pb5 pin: can2 in reception mode can2_tx pin output pb13 pin: can2 in transmission mode i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111010x (where x = 0 for write and x = 1 for read). i2c1_scl pin input/output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/output pb7 pin: data line is used in open-drain mode. i2c2 bootloader i2c2 enabled the i2c2 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111010x (where x = 0 for write and x = 1 for read). i2c2_scl pin input/output pf1 pin: clock line is used in open-drain mode. i2c2_sda pin input/output pf0 pin: data line is used in open-drain mode. table 24. stm32f40xxx/41xxx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 55/155 AN2606 stm32f40xxx/41xxx devices bootloader 154 i2c3 bootloader i2c3 enabled the i2c3 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111010x (where x = 0 for write and x = 1 for read). i2c3_scl pin input/output pa8 pin: clock line is used in open-drain mode. i2c3_sda pin input/output pc9 pin: data line is used in open-drain mode. spi1 bootloader spi1 enabled the spi1 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi1_mosi pin input pa7 pin: slave data input line, used in push-pull pull-down mode spi1_miso pin output pa6 pin: slave data output line, used in push-pull pull-down mode spi1_sck pin input pa5 pin: slave clock line, used in push-pull pull-down mode spi1_nss pin input pa4 pin: slave chip select pin used in push-pull pull-down mode. spi2 bootloader spi2 enabled the spi2 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi2_mosi pin input pi3 pin: slave data input line, used in push- pull pull-down mode spi2_miso pin output pi2 pin: slave data output line, used in push-pull pull-down mode spi2_sck pin input pi1 pin: slave clock line, used in push-pull pull-down mode spi2_nss pin input pi0 pin: slave chip select pin used in push-pull pull-down mode. dfu bootloader usb enabled usb otg fs configured in forced device mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line no external pull-up resistor is required can2 and dfu bootloaders tim11 enabled this timer is used to determine the value of the hse. once the hse frequency is determined, the system clock is configured to 60 mhz using pll and hse. table 24. stm32f40xxx/41xxx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32f40xxx/41xxx devices bootloader AN2606 56/155 docid13801 rev 21 the system clock is derived from the embedded internal high-speed rc for usartx, i2cx and spix bootloaders. this internal clock is also used for can and dfu (usb fs device) but only for the selection phase. an external clock multiple of 1 mhz (between 4 and 26 mhz) is required for can and dfu bootloader execution after the selection phase. docid13801 rev 21 57/155 AN2606 stm32f40xxx/41xxx devices bootloader 154 11.2.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 15. bootloader v9.x selection for stm32f40xxx/41xxx 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v q r < h v * h q h u d w h 6 \ v w h p u h v h w & r q i l j x u h 8 6 % 2 7 * ) 6 g h y l f h 8 6 % f d e o h ' h w h f w h g [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v + 6 ( g h w h f w h g \ h v q r , & [ $ g g u h v v ' h w h f w h g [ ( [ h f x w h % / b , & b / r r s i r u , & [ v} v} ? ? & r q i l j x u h , & [ & r q i l j x u h 6 3 , [ ' l v d e o h d o o l q w h u u x s w v r x u f h v 6 3 , [ g h w h f w v 6 \ q f k u r p h f k d q l v p v} ( [ h f x w h % / b 6 3 , b / r r s i r u 6 3 , [ ? ? ' l v d e o h d o o l q w h u u x s w v r x u f h v ) u d p h g h w h f w h g r q & $ 1 [ v} + 6 ( g h w h f w h g ( [ h f x w h % / b & $ 1 b / r r s i r u & $ 1 [ & r q i l j x u h & $ 1 ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] \ h v v} stm32f40xxx/41xxx devices bootloader AN2606 58/155 docid13801 rev 21 11.2.3 bootloader version the following table lists the stm32f40xxx/ 41xxx devices v9.x bootloader versions. table 25. stm32f40xxx/41xxx bootloader v9.x versions bootloader version number description known limitations v9.0 this bootloader is an updated version of bootloader v3.1. this new version of bootloader supports i2c1, i2c2, i2c3, spi1 and spi2 interfaces. the ram used by this bootloader is increased from 8kb to 12kb. the id of this bootloader is 0x90. the connection time is increased. ? for the usart interface, two consecutive nacks (instead of 1 nack) are sent when a read memory or write memory command is sent and the rdp level is active. ? for the can interface, the write unprotect command is not functional. instead you can use write memory command and write directly to the option bytes in order to disable the write protection. docid13801 rev 21 59/155 AN2606 stm32f05xxx and stm32f030x8 devices bootloader 154 12 stm32f05xxx and stm32f 030x8 devices bootloader 12.1 bootloader configuration the stm32f05xxx and stm32f030x8 devices boot loader is activated by applying pattern2 (described in table 2: bootloader activation patterns ). the following table shows the hardware resources used by this bootloader. the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. note: after the stm32f05xxx and stm32f030x8 devices have booted in bootloader mode, the serial wire debug (swd) communication is no more possible until the system is reset, because swd uses pa14 pin (swclk) which is already used by the bootloader (usart2_tx). table 26. stm32f05xxx and stm32f030x8 devices configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 24 mhz (using pll clocked by hsi). 1 flash wait state. ram - 2 kbytes starting from address 0x20000000 are used by the bootloader firmware. system memory - 3 kbytes starting from address 0x1fffec00, contain the bootloader firmware. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset in case the hardware iwdg option was previously enabled by the user. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode. usart1_tx pin output pa9 pin: usart1 in transmission mode. usart2 bootloader usart2 enabled once initialized, the usart2 configuration is 8 bits, even parity and 1 stop bit. usart2_rx pin input pa15 pin: usart2 in reception mode. usart2_tx pin output pa14 pin: usart2 in transmission mode. usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host. stm32f05xxx and stm32f030x8 devices bootloader AN2606 60/155 docid13801 rev 21 12.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 16. bootloader selection for stm32f05xxx and stm32f030x8 devices 12.3 bootloader version the following table lists the stm32f05xxx an d stm32f030x8 devices bootloader versions. 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ 1 r ' l v d e o h d o o l q w h u u x s w v r x u f h v < h v table 27. stm32f05xxx and stm32f030x8 devices bootloader versions bootloader version number description known limitations v2.1 initial bootloader version when the user application configures a value of hsi trim bits (in rcc_cr register) and then jumps to the bootloader, the hsitrim value is set (0) at bootloader startup. for the usart interface, two consecutive nacks instead of 1 nack are sent when a read memory or write memory command is sent and the rdp level is active. docid13801 rev 21 61/155 AN2606 stm32f03xxx devices bootloader 154 13 stm32f03xxx devices bootloader 13.1 bootloader configuration the stm32f03xxx bootloader is activated by applying pattern2 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. note: after the stm32f03xxx devices has booted in bootloader mode, serial wire debug (swd) communication is no longer possible until th e system is reset. this is because the swd uses the pa14 pin (swclk) which is already used by the bootloader (usart1_tx). table 28. stm32f03xxx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 24 mhz (using pll clocked by hsi). 1 flash wait state. ram - 2 kbytes starting from address 0x20000000 are used by the bootloader firmware. system memory - 3 kbytes starting from address 0x1fffec00 contain the bootloader firmware. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset in case the hardware iwdg option was previously enabled by the user. usart1 bootloader (on pa10/pa9) usart1 enabled once initialized, the usart1 configuration is 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode. usart1_tx pin output pa9 pin: usart1 in transmission mode. usart1 bootloader (on pa14/pa15) usart1 enabled once initialized, the usart1 configuration is 8 bits, even parity and 1 stop bit. usart1_rx pin input pa15 pin: usart1 in reception mode. usart1_tx pin output pa14 pin: usart1 in transmission mode. usart1 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host. stm32f03xxx devices bootloader AN2606 62/155 docid13801 rev 21 13.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 17. bootloader selection for stm32f03xxx devices 13.3 bootloader version the following table lists the stm32f03xxx devices bootloader versions. 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ 1 r ' l v d e o h d o o l q w h u u x s w v r x u f h v < h v table 29. stm32f03xxx bootloader versions bootloader version number description known limitations v1.0 initial bootloader version for the usart interface, two consecutive nacks instead of 1 nack are sent when a read memory or write memory command is sent and the rdp level is active. docid13801 rev 21 63/155 AN2606 stm32f373xx devices bootloader 154 14 stm32f373xx devices bootloader 14.1 bootloader configuration the stm32f373xx bootloader is activated by applying pattern2 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 30. stm32f373xx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled at startup, the system clock frequency is configured to 48 mhz using the hsi. if an external clock (hse) is not present, the system is kept clocked from the hsi. hse enabled the external clock can be used for all bootloader interfaces and should have one the following values 24, 18,16, 12, 9, 8, 6, 4, 3 mhz. the pll is used to generate the usb 48 mhz clock and the 48 mhz clock for the system clock. - the clock security s ystem (css) interrupt is enabled for the dfu bootloader. any failure (or removal) of the external clock generates system reset. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). system memory - 8 kbytes starting from address 0x1fffd800. this area contains the bootloader firmware ram - 5 kbytes starting from address 0x20000000 are used by the bootloader firmware. usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloader. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode stm32f373xx devices bootloader AN2606 64/155 docid13801 rev 21 the bootloader has two case of operation depe nding on the presence of the external clock (hse) at bootloader startup: ? if hse is present and has a value of 24, 18, 16, 12, 9, 8, 6, 4 or 3 mhz, the system clock is configured to 48 mhz with hse as clock source. the dfu interface, usart1 and usart2 are functional and can be used to communicate with the bootloader device. ? if hse is not present, the hsi is kept as default clock source and only usart1 and usart2 are functional. note: the external clock (hse) must be kept if it?s connected at bootloader startu p because it will be used as system clock source. usart2 bootloader usart2 enabled once initialized, the usart2 configuration is: 8 bits, even parity and 1 stop bit. the usart2 uses its remapped pins. usart2_rx pin input pd6 pin: usart2 in reception mode usart2_tx pin output pd5 pin: usart2 in transmission mode dfu bootloader usb enabled usb used in fs mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line an external pull-up re sistor 1.5 kohm must be connected to usb_dp pin. table 30. stm32f373xx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 65/155 AN2606 stm32f373xx devices bootloader 154 14.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 18. bootloader selection for stm32f373xx devices 14.3 bootloader version the following table lists the stm32f373xx devices bootloader versions. 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n [ ) u h f h l y h g r q 8 6 $ 5 7 b [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ & r q i l j x u h 8 6 % 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] x v l q j + 6 ( ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v 1 r 1 r ' l v d e o h d o o l q w h u u x s w v r x u f h v < h v 8 6 % f r q i l j x u h g d q g f d e o h ' h w h f w h g + 6 ( 0 + ] e} ? ? ? ? & r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] x v l q j + 6 , 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n table 31. stm32f373xx bootloader versions bootloader version number description known limitations v4.1 initial bootloader version none stm32f302xb(c)/303xb(c) devices bootloader AN2606 66/155 docid13801 rev 21 15 stm32f302xb(c)/303xb(c) devices bootloader 15.1 bootloader configuration the stm32f302xb(c)/303xb(c) bootloader is acti vated by applying pattern2 (described in table 2: bootloader activation patterns ). the following table shows the hardware resources used by this bootloader. table 32. stm32f302xb(c)/303xb(c) configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled at startup, the system clock frequency is configured to 48 mhz using the hsi. if an external clock (hse) is not present, the system is kept clocked from the hsi. hse enabled the external clock can be used for all bootloader interfaces and should have one the following values 24, 18,16, 12, 9, 8, 6, 4, 3 mhz. the pll is used to generate the usb 48 mhz clock and the 48 mhz clock for the system clock. - the clock security s ystem (css) interrupt is enabled for the dfu bootloader. any failure (or removal) of the external clock generates system reset. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). system memory - 8 kbytes starting from address 0x1fffd800. this area contains the bootloader firmware ram - 5 kbytes starting from address 0x20000000 are used by the bootloader firmware. usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloader. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode docid13801 rev 21 67/155 AN2606 stm32f302xb(c)/303xb(c) devices bootloader 154 the bootloader has two case of operation depe nding on the presence of the external clock (hse) at bootloader startup: ? if hse is present and has a value of 24, 18, 16, 12, 9, 8, 6, 4 or 3 mhz, the system clock is configured to 48 mhz with hse as clock source. the dfu interface, usart1 and usart2 are functional and can be used to communicate with the bootloader device. ? if hse is not present, the hsi is kept as default clock source and only usart1 and usart2 are functional. the external clock (hse) must be kept if it?s connected at bootloader startup because it will be used as system clock source. usart2 bootloader usart2 enabled once initialized, the usart2 configuration is: 8 bits, even parity and 1 stop bit. the usart2 uses its remapped pins. usart2_rx pin input pd6 pin: usart2 in reception mode usart2_tx pin output pd5 pin: usart2 in transmission mode dfu bootloader usb enabled usb used in fs mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line an external pull-up re sistor 1.5 kohm must be connected to usb_dp pin. table 32. stm32f302xb(c)/303xb(c) configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32f302xb(c)/303xb(c) devices bootloader AN2606 68/155 docid13801 rev 21 15.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 19. bootloader selection for stm32f302xb(c)/303xb(c) devices 15.3 bootloader version the following table lists the stm32f302xb(c)/303xb(c) devices bootloader versions. 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n [ ) u h f h l y h g r q 8 6 $ 5 7 b [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ & r q i l j x u h 8 6 % 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] x v l q j + 6 ( ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v 1 r 1 r ' l v d e o h d o o l q w h u u x s w v r x u f h v < h v 8 6 % f r q i l j x u h g d q g f d e o h ' h w h f w h g + 6 ( 0 + ] e} ? ? ? ? & r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] x v l q j + 6 , 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n table 33. stm32f302xb(c)/303xb(c) bootloader versions bootloader version number description known limitations v4.1 initial bootloader version none docid13801 rev 21 69/155 AN2606 stm32f378xx devices bootloader 154 16 stm32f378xx devices bootloader 16.1 bootloader configuration the stm32f378xx bootloader is activated by applying pattern2 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 34. stm32f378xx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 8 mhz using the hsi. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). window feature is disabled. system memory - 8 kbytes starting from address 0x1fffd800. this area contains the bootloader firmware ram - 4 kbytes starting from address 0x20000000 are used by the bootloader firmware. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode. usart1_tx pin output pa9 pin: usart1 in transmission mode. usart2 bootloader usart2 enabled once initialized, the usart2 configuration is: 8 bits, even parity and 1 stop bit. the usart2 uses its remapped pins. usart2_rx pin input pd6 pin: usart2 in reception mode. usart2_tx pin output pd5 pin: usart2 in transmission mode. usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloader. i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filt er on. slave 7-bit address: 0b0110111x (where x = 0 for write and x = 1 for read). i2c1_scl pin input/ output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/ output pb7 pin: data line is used in open-drain mode. stm32f378xx devices bootloader AN2606 70/155 docid13801 rev 21 the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. 16.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 20. bootloader selection for stm32f378xx devices 16.3 bootloader version the following table lists the stm32f378xx devices bootloader versions. initial bootloader version 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n [ ) u h f h l y h g r q 8 6 $ 5 7 b [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ & r q i l j x u h , & [ ( [ h f x w h % / b , & b / r r s i r u , & [ 1 r 1 r < h v , & $ g g u h v v g h w h f w h g ? ? ]?o oo ]v? ???? ?}? ? table 35. stm32f378xx bootloader versions bootloader version number description known limitations v5.0 for usart1 and usart2 interfaces, the maximum baudrate supported by the bootloader is 57600 baud. docid13801 rev 21 71/155 AN2606 stm32f358xx devices bootloader 154 17 stm32f358xx devices bootloader 17.1 bootloader configuration the stm32f358xx bootloader is activated by applying pattern2 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 36. stm32f358xx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 8 mhz using the hsi. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). window feature is disabled. system memory - 8 kbytes starting from address 0x1fffd800. this area contains the bootloader firmware. ram - 5 kbytes starting from address 0x20000000 are used by the bootloader firmware. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode. usart1_tx pin output pa9 pin: usart1 in transmission mode. usart2 bootloader usart2 enabled once initialized, the usart2 configuration is: 8 bits, even parity and 1 stop bit. the usart2 uses its remapped pins. usart2_rx pin input pd6 pin: usart2 in reception mode. usart2_tx pin output pd5 pin: usart2 in transmission mode. usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloader. i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filt er on. slave 7-bit address: 0b0110111x (where x = 0 for write and x = 1 for read) i2c1_scl pin input/ output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/ output pb7 pin: data line is used in open-drain mode. stm32f358xx devices bootloader AN2606 72/155 docid13801 rev 21 the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. 17.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 21. bootloader selection for stm32f358xx devices 17.3 bootloader version the following table lists the stm32f358xx devices bootloader versions. initial bootloader version 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n [ ) u h f h l y h g r q 8 6 $ 5 7 b [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ & r q i l j x u h , & [ ( [ h f x w h % / b , & b / r r s i r u , & [ 1 r 1 r < h v , & $ g g u h v v g h w h f w h g ? ? ]?o oo ]v? ???? ?}? ? table 37. stm32f358xx bootloader versions bootloader version number description known limitations v5.0 for usart1 and usart2 interfaces, the maximum baudrate supported by the bootloader is 57600 baud. docid13801 rev 21 73/155 AN2606 stm32f42xxx/43xxx devices bootloader 154 18 stm32f42xxx/43xxx devices bootloader 18.1 bootloader v7.x 18.1.1 bootloader configuration the stm32f42xxx/43xxx bootloader is activa ted by applying pattern5 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 38. stm32f42xxx/43xxx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 24 mhz using the pll. the hsi clock source is used at startup (interface detection phase) and when usart or i2c interfaces are selected (once can or dfu bootloader is selected, the clock source will be derived from the external crystal). hse enabled the system clock frequency is 60 mhz. the hse clock source is used only when the can or the dfu (usb fs device) interfaces are selected. the external clock must provide a frequency multiple of 1 mhz and ranging from 4 mhz to 26 mhz. - the clock security system (css) interrupt is enabled for the can and dfu bootloaders. any failure (or removal) of the external clock gene rates system reset. ram - 8 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 30424 bytes starting from address 0x1fff0000, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - voltage range is set to [1.62 v, 2.1 v]. in this range internal flash write operations are allowed only in byte format (half-word, word and double-word operations are not allowed). the voltage range can be configured in run time using bootloader commands. stm32f42xxx/43xxx devices bootloader AN2606 74/155 docid13801 rev 21 usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8 bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart3 bootloader (on pb10/pb11) usart3 enabled once initialized the usart3 configuration is: 8 bits, even parity and 1 stop bit usart3_rx pin input pb11 pin: usart3 in reception mode usart3_tx pin output pb10 pin: usart3 in transmission mode usart3 bootloader (on pc10/pc11) usart3 enabled once initialized the usart3 configuration is: 8 bits, even parity and 1 stop bit usart3_rx pin input pc11 pin: usart3 in reception mode usart3_tx pin output pc10 pin: usart3 in transmission mode usart1 and usart3 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. can2 bootloader can2 enabled once initialized the can2 configuration is: baudrate 125 kbps, 11-bit identifier. note: can1 is clocked during can2 bootloader execution because can1 manages the communication between can2 and sram. can2_rx pin input pb5 pin: can2 in reception mode can2_tx pin output pb13 pin: can2 in transmission mode i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111000x (where x = 0 for write and x = 1 for read). i2c1_scl pin input/output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/output pb9 pin: data line is used in open-drain mode. dfu bootloader usb enabled usb otg fs configured in forced device mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line no external pull-up resistor is required can2 and dfu bootloaders tim11 enabled this timer is used to determine the value of the hse. once the hse frequency is determined, the system clock is configured to 60 mhz using pll and hse. table 38. stm32f42xxx/43xxx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 75/155 AN2606 stm32f42xxx/43xxx devices bootloader 154 the system clock is derived from the embed ded internal high-speed rc for usartx and i2cx bootloaders. this internal clock is also used for can and dfu (usb fs device) but only for the selection phase. an external clock multiple of 1 mhz (between 4 and 26 mhz) is required for can and dfu bootloader execution after the selection phase. stm32f42xxx/43xxx devices bootloader AN2606 76/155 docid13801 rev 21 18.1.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 22. dual bank boot implementation for stm32f42xxx/43xxx bootloader v7.x 0 6 9 6 \ v w h p 5 h v h w /( }}? a v} ? ? w?}? ?]}v o o? vo & r q w l q x h % r r w o r d g h u h [ h f x w l r q v} /( so }( (]??? ? ?? }( vl? ]? ]?z]v ]v?x ^ z d ? ?? ^ ? vl ^? ?} vl? ^ ? vl ^? ?} vl ? ? v} :u? ?} ? ? } ]v vl? :u? ?} ? ? } ]v vl ? ? /( so }( (]??? ? ?? }( vl? ]? ]?z]v ]v?x ^ z d ? ?? ^ ? vl ^? ?} vl? ^ ? vl ^? ?} vl ? ? :u? ?} ? ? } ]v vl? :u? ?} ? ? } ]v vl w?}? ?]}v o o? vo /( so }( (]??? ? ?? }( vl ]? ]?z]v ]v?x ^ z d ? ?? ? ? v} v} & r q w l q x h % r r w o r d g h u h [ h f x w l r q v} ? ? docid13801 rev 21 77/155 AN2606 stm32f42xxx/43xxx devices bootloader 154 figure 23. bootloader v7.x selection for stm32f42xxx/43xxx 0 6 9 % r r w o r d g h u 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v 1 r < h v * h q h u d w h 6 \ v w h p u h v h w & r q i l j x u h 8 6 % 2 7 * ) 6 g h y l f h ) u d p h g h w h f w h g r q & $ 1 [ 1 r + 6 ( g h w h f w h g ( [ h f x w h % / b & $ 1 b / r r s i r u & $ 1 8 6 % f d e o h ' h w h f w h g [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v 1 r & r q i l j x u h & $ 1 + 6 ( g h w h f w h g ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v \ h v \ h v 1 r 1 r 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] e} & r q i l j x u h , & [ , & $ g g u h v v ' h w h f w h g ( [ h f x w h % / b , & b / r r s i r u , & [ z ? stm32f42xxx/43xxx devices bootloader AN2606 78/155 docid13801 rev 21 18.1.3 bootloader version the following table lists the stm32f42xxx/ 43xxx devices bootload er v7.x versions. initial bootloader version for the can interface, the write unprotect comma nd is not functional. instead you can use write memory command and write directly to the option bytes in order to disable the write protection. 18.2 bootloader v9.x 18.2.1 bootloader configuration the stm32f42xxx/43xxx bootloader is activa ted by applying pattern5 (described in table 2: bo otloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 39. stm32f42xxx/43xxx bootloader v7.x versions bootloader version number description known limitations v7.0 docid13801 rev 21 79/155 AN2606 stm32f42xxx/43xxx devices bootloader 154 table 40. stm32f42xxx/43xxx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 60 mhz using the pll. the hsi clock source is used at startup (interface detection phase) and when usart or spi or i2c interfaces are selected (once can or dfu bootloader is selected, the clock source will be derived from the external crystal). hse enabled the system clock frequency is 60 mhz. the hse clock source is used only when the can or the dfu (usb fs device) interfaces are selected. the external clock must provide a frequency multiple of 1 mhz and ranging from 4 mhz to 26 mhz. - the clock security s ystem (css) interrupt is enabled for the can and dfu bootloaders. any failure (or removal) of the external clock generates system reset. ram - 12 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 30424 bytes starting from address 0x1fff0000, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - voltage range is set to [1.62 v, 2.1 v]. in this range internal flash write operations are allowed only in byte format (half-word, word and double-word operations are not allowed). the voltage range can be configured in run time using bootloader commands. usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart3 bootloader (on pb10/pb11) usart3 enabled once initialized the usart3 configuration is: 8-bits, even parity and 1 stop bit usart3_rx pin input pb11 pin: usart3 in reception mode usart3_tx pin output pb10 pin: usart3 in transmission mode stm32f42xxx/43xxx devices bootloader AN2606 80/155 docid13801 rev 21 usart3 bootloader (on pc10/pc11) usart3 enabled once initialized the usart3 configuration is: 8-bits, even parity and 1 stop bit usart3_rx pin input pc11 pin: usart3 in reception mode usart3_tx pin output pc10 pin: usart3 in transmission mode usart1 and usart3 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. can2 bootloader can2 enabled once initialized the can2 configuration is: baudrate 125 kbps, 11-bit identifier. note: can1 is clocked during can2 bootloader execution because can1 manages the communication between can2 and sram. can2_rx pin input pb5 pin: can2 in reception mode can2_tx pin output pb13 pin: can2 in transmission mode i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111000x (where x = 0 for write and x = 1 for read). i2c1_scl pin input/output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/output pb9 pin: data line is used in open-drain mode. i2c2 bootloader i2c2 enabled the i2c2 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111000x (where x = 0 for write and x = 1 for read). i2c2_scl pin input/output pf1 pin: clock line is used in open-drain mode. i2c2_sda pin input/output pf0 pin: data line is used in open-drain mode. i2c3 bootloader i2c3 enabled the i2c3 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111000x (where x = 0 for write and x = 1 for read). i2c3_scl pin input/output pa8 pin: clock line is used in open-drain mode. i2c3_sda pin input/output pc9 pin: data line is used in open-drain mode. table 40. stm32f42xxx/43xxx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 81/155 AN2606 stm32f42xxx/43xxx devices bootloader 154 spi1 bootloader spi1 enabled the spi1 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi1_mosi pin input pa7 pin: slave data input line, used in push-pull pull-down mode spi1_miso pin output pa6 pin: slave data output line, used in push-pull pull-down mode spi1_sck pin input pa5 pin: slave clock line, used in push-pull pull-down mode spi1_nss pin input pa4 pin: slave chip select pin used in push-pull pull-down mode. spi2 bootloader spi2 enabled the spi2 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi2_mosi pin input pi3 pin: slave data input line, used in push- pull pull-down mode spi2_miso pin output pi2 pin: slave data output line, used in push-pull pull-down mode spi2_sck pin input pi1 pin: slave clock line, used in push-pull pull-down mode spi2_nss pin input pi0 pin: slave chip select pin used in push-pull pull-down mode. spi4 bootloader spi4 enabled the spi4 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi4_mosi pin input pe14 pin: slave data input line, used in push-pull pull-down mode spi4_miso pin output pe13 pin: slave data output line, used in push-pull pull-down mode sp4_sck pin input pe12 pin: slave clock line, used in push- pull pull-down mode spi4_nss pin input pe11 pin: slave chip select pin used in push-pull pull-down mode. table 40. stm32f42xxx/43xxx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32f42xxx/43xxx devices bootloader AN2606 82/155 docid13801 rev 21 the system clock is derived from the embedded internal high-speed rc for usartx, i2cx and spix bootloaders. this internal clock is also used for can and dfu (usb fs device) but only for the selection phase. an external clock multiple of 1 mhz (between 4 and 26 mhz) is required for can and dfu bootloader execution after the selection phase. dfu bootloader usb enabled usb otg fs configured in forced device mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line no external pull-up resistor is required can2 and dfu bootloaders tim11 enabled this timer is used to determine the value of the hse. once the hse frequency is determined, the system clock is configured to 60 mhz using pll and hse. table 40. stm32f42xxx/43xxx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 83/155 AN2606 stm32f42xxx/43xxx devices bootloader 154 18.2.2 bootloader selection the figures below show the bootloader selection mechanism. figure 24. dual bank boot implementation for stm32f42xxx/43xxx bootloader v9.x 0 6 9 6 \ v w h p 5 h v h w /( }}? a v} ? ? w?}? ?]}v o o? vo & r q w l q x h % r r w o r d g h u h [ h f x w l r q v} /( so }( (]??? ? ?? }( vl? ]? ]?z]v ]v?x ^ z d ? ?? ^ ? vl ^? ?} vl? ^ ? vl ^? ?} vl ? ? v} :u? ?} ? ? } ]v vl? :u? ?} ? ? } ]v vl ? ? /( so }( (]??? ? ?? }( vl? ]? ]?z]v ]v?x ^ z d ? ?? ^ ? vl ^? ?} vl? ^ ? vl ^? ?} vl ? ? :u? ?} ? ? } ]v vl? :u? ?} ? ? } ]v vl w?}? ?]}v o o? vo /( so }( (]??? ? ?? }( vl ]? ]?z]v ]v?x ^ z d ? ?? ? ? v} v} & r q w l q x h % r r w o r d g h u h [ h f x w l r q v} ? ? stm32f42xxx/43xxx devices bootloader AN2606 84/155 docid13801 rev 21 figure 25. bootloader v9.x selection for stm32f42xxx/43xxx 0 6 9 % r r w o r d g h u 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v 1 r < h v * h q h u d w h 6 \ v w h p u h v h w & r q i l j x u h 8 6 % 2 7 * ) 6 g h y l f h ) u d p h g h w h f w h g r q & $ 1 [ 1 r + 6 ( g h w h f w h g ( [ h f x w h % / b & $ 1 b / r r s i r u & $ 1 8 6 % f d e o h ' h w h f w h g [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v 1 r & r q i l j x u h & $ 1 + 6 ( g h w h f w h g ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v \ h v \ h v 1 r 1 r 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] e} & r q i l j x u h 6 3 , [ , & $ g g u h v v ' h w h f w h g ( [ h f x w h % / b , & b / r r s i r u , & [ z ? 1 r ^?vz?} u zv]?u ? ? }v ^ w /? ( [ h f x w h % / b 6 3 , b / r r s i r u 6 3 , [ z ? & r q i l j x u h , & [ docid13801 rev 21 85/155 AN2606 stm32f42xxx/43xxx devices bootloader 154 18.2.3 bootloader version the following table lists the stm32f42xxx/ 43xxx devices bootload er v9.x versions. table 41. stm32f42xxx/43xxx bootloader v9.x versions bootloader version number description known limitations v9.0 this bootloader is an updated version of bootloader v7.0. this new version of bootloader supports i2c2, i2c3, spi1, spi2 and spi4 interfaces. the ram used by this bootloader is increased from 8kb to 12kb. the id of this bootloader is 0x90 the connection time is increased. none v9.1 this bootloader is an updated version of bootloader v9.0. this new version implements the new i2c no-stretch commands (i2c protocol v1.1) and the capability of disabling pcrop when rdp1 is enabled with readoutunprotect command for all protocols(usb, usart, can, i2c and spi). the id of this bootloader is 0x91 for the can interface, the write unprotect command is not functional. instead you can use write memory command and write directly to the option bytes in order to disable the write protection. stm32f04xxx devices bootloader AN2606 86/155 docid13801 rev 21 19 stm32f04xxx devices bootloader 19.1 bootloader configuration the stm32f04xxx bootloader is activated by applying pattern6 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 42. stm32f04xxx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 48 mhz with hsi 48 mhz as clock source. - the clock recovery system (crs) is enabled for the dfu bootloaders to allow usb to be clocked by hsi 48 mhz. ram - 6 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 13 kbytes starting from address 0x1fffc400, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized the usart2 configuration is: 8-bits, even parity and 1 stop bit usart2_rx pin input pa15 pin: usart2 in reception mode usart2_tx pin output pa14 pin: usart2 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. docid13801 rev 21 87/155 AN2606 stm32f04xxx devices bootloader 154 note: after the stm32f04xxx devices have booted in bootloader mode using usart2, the serial wire debug (swd) communication is no more po ssible until the system is reset, because swd uses pa14 pin (swclk) which is already used by the bootloader (usart2_rx). the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. i2c1 bootloader i2c1 enabled the i2c1configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111110x (where x = 0 for write and x = 1 for read). i2c1_scl pin input/output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/output pb7 pin: data line is used in open-drain mode. dfu bootloader usb enabled usb used in fs mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line no external pull-up resistor is required. table 42. stm32f04xxx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32f04xxx devices bootloader AN2606 88/155 docid13801 rev 21 19.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 26. bootloader selection for stm32f04xxx 19.3 bootloader version the following table lists the stm32f04xxx devices bootloader versions: 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v 1 r }v(]p? /? ? [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ]?o oo ]v? ???? ?}? ? v }?z ? ]v? ?( ? o}l[? < h v < h v , & [ $ g g u h v v ' h w h f w h g ( [ h f x w h % / b , & b / r r s i r u , & [ e} z ? }v(]p? h ^ & ^ ] ' l v d e o h d o o l q w h u u x s w v r x u f h v d q g r w k h u l q w h u i d f h v f o r f n ? v 1 r ]?o }?z ? ]v? ?( ? o}l[? 8 6 % ' h w h f w h g table 43. stm32f04xxx bootloader versions bootloader version number description known limitations v10.0 initial bootloader version when the user application configures a value of hsi trim bits (in rcc_cr register) and then jumps to the bootloader, the hsitrim value is set to (0) at bootloader startup docid13801 rev 21 89/155 AN2606 stm32f07xxx devices bootloader 154 20 stm32f07xxx devices bootloader 20.1 bootloader configuration the stm32f07xxx bootloader is activated by applying pattern2 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 44. stm32f07xxx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 48 mhz with hsi 48 mhz as clock source. - the clock recovery system (crs) is enabled for the dfu bootloaders to allow usb to be clocked by hsi 48 mhz. ram - 6 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 12 kbytes starting from address 0x1fffc800, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized the usart2 configuration is: 8-bits, even parity and 1 stop bit usart2_rx pin input pa15 pin: usart2 in reception mode usart2_tx pin output pa14 pin: usart2 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. stm32f07xxx devices bootloader AN2606 90/155 docid13801 rev 21 note: after the stm32f07xxx devices have booted in bootloader mode using usart2, the serial wire debug (swd) communication is no more po ssible until the system is reset, because swd uses pa14 pin (swclk) which is already used by the bootloader (usart2_rx). the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111011x (where x = 0 for write and x = 1 for read) i2c1_scl pin input/output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/output pb7 pin: data line is used in open-drain mode. dfu bootloader usb enabled usb used in fs mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line no external pull-up resistor is required. table 44. stm32f07xxx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 91/155 AN2606 stm32f07xxx devices bootloader 154 20.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 27. bootloader selection for stm32f07xxx 20.3 bootloader version the following table lists the stm32f07xxx devices bootloader versions: 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v 1 r }v(]p? /? ? [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ]?o oo ]v? ???? ?}? ? v }?z ? ]v? ?( ? o}l[? < h v < h v , & [ $ g g u h v v ' h w h f w h g ( [ h f x w h % / b , & b / r r s i r u , & [ e} z ? }v(]p? h ^ & ^ ] ' l v d e o h d o o l q w h u u x s w v r x u f h v d q g r w k h u l q w h u i d f h v f o r f n ? v 1 r ]?o }?z ? ]v? ?( ? o}l[? 8 6 % ' h w h f w h g table 45. stm32f07xxx bootloader versions bootloader version number description known limitations v10.1 initial bootloader version when the user application configures a value of hsi trim bits (in rcc_cr register) and then jumps to the bootloader, the hsitrim value is set to (0) at bootloader startup stm32f301xx/302x4(6/8) devices bootloader AN2606 92/155 docid13801 rev 21 21 stm32f301xx/302x4(6/8) devices bootloader 21.1 bootloader configuration the stm32f301xx/302x4(6/8) bootloader is activated by applying pattern2 (described in table 2: bootloader activation patterns ). the following table shows the hardware resources used by this bootloader. table 46. stm32f301xx/302x4(6/8) configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 48 mhz with hsi 48 mhz as clock source. hse enabled the external clock can be used for all bootloader interfaces and should have one the following values 24, 18,16, 12, 9, 8, 6, 4, 3 mhz. the pll is used to generate the usb 48 mhz clock and the 48 mhz clock for the system clock. - the clock security system (css) interrupt is enabled for the dfu bootloader. any failure (or removal) of the external clock generates system reset. ram - 6 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 8 kbytes starting from address 0x1fffd800, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized the usart2 configuration is: 8-bits, even parity and 1 stop bit usart2_rx pin input pa3 pin: usart2 in reception mode usart2_tx pin output pa2 pin: usart2 in transmission mode docid13801 rev 21 93/155 AN2606 stm32f301xx/302x4(6/8) devices bootloader 154 the bootloader has two case of operation depe nding on the presence of the external clock (hse) at bootloader startup: ? if hse is present and has a value of 24, 18, 16, 12, 9, 8, 6, 4 or 3 mhz, the system clock is configured to 48 mhz with hse as clock source. the dfu interface, usart1 and usart2 are functional and can be used to communicate with the bootloader device. ? if hse is not present, the hsi is kept as default clock source and only usart1 and usart2 are functional. the external clock (hse) must be kept if it?s connected at bootloader startup because it will be used as system clock source. usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. dfu bootloader usb enabled usb used in fs mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line an external pull-up re sistor 1.5 kohm must be connected to usb_dp pin. table 46. stm32f301xx/302x4(6/8) configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32f301xx/302x4(6/8) devices bootloader AN2606 94/155 docid13801 rev 21 21.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 28. bootloader select ion for stm32f301xx/302x4(6/8) 21.3 bootloader version the following table lists the stm32f301xx/3 02x4(6/8) devices bootloader versions: 0 6 9 6 \ v w h p 5 h v h w & r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] x v l q j + 6 , ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v q r & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ]?o oo ]v? ???? ?}? ? v }?z ? ]v? ?( ? o}l[? \ h v v} z }v(]p? ^??? u o}l ?} e? d , ?]vp , ^ ]?o }?z ? ]v? ?( ? o}l[? + 6 ( 0 + ] " }v(]p? h ^ & ^ ] ^??? u /v]? ~ o}lu ' w / k?u , : ' * 6 \ v 7 l f n ^??? u /v]? ~ o}lu ' w / k?u , : ' * 6 \ v 7 l f n z ? e} [ ) u h f h l y h g r q 8 6 $ 5 7 [ 8 6 % f d e o h ' h w h f w h g 8 6 % f r q i l j x u h g ? ? table 47. stm32f301xx/302x4(6/8) bootloader versions bootloader version number description known limitations v4.0 initial bootloader version none docid13801 rev 21 95/155 AN2606 stm32f318xx devices bootloader 154 22 stm32f318xx devices bootloader 22.1 bootloader configuration the stm32f318xx bootloader is activated by applying pattern2 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 48. stm32f318xx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 60 mhz with hsi 8 mhz as clock source. ram - 6 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 8 kbytes starting from address 0x1fffd800, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized the usart2 configuration is: 8-bits, even parity and 1 stop bit usart2_rx pin input pa3 pin: usart2 in reception mode usart2_tx pin output pa2 pin: usart2 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111101x (where x = 0 for write and x = 1 for read) i2c1_scl pin input/output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/output pb7 pin: data line is used in open-drain mode. stm32f318xx devices bootloader AN2606 96/155 docid13801 rev 21 the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. 22.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 29. bootloader selection for stm32f318xx i2c3 bootloader i2c3 enabled the i2c3 configuration is: i2c speed: up to 400 khz, 7-bit address,slave mode, analog filter on. slave 7-bit address: 0b0111101x (where x = 0 for write and x = 1 for read) and digital filter disabled. i2c3_scl pin input/output pa8 pin: clock line is used in open-drain mode. i2c3_sda pin input/output pb5 pin: data line is used in open-drain mode. table 48. stm32f318xx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n [ ) u h f h l y h g r q 8 6 $ 5 7 b [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ & r q i l j x u h , & [ ( [ h f x w h % / b , & b / r r s i r u , & [ 1 r 1 r < h v , & $ g g u h v v g h w h f w h g ? ? ]?o oo ]v? ???? ?}? ? docid13801 rev 21 97/155 AN2606 stm32f318xx devices bootloader 154 22.3 bootloader version the following table lists the stm32f318xx devices bootloader versions: table 49. stm32f318xx bootloader versions bootloader version number description known limitations v5.0 initial bootloader version none stm32f303x4(6/8)/334xx/328xx devices bootloader AN2606 98/155 docid13801 rev 21 23 stm32f303x4(6/8)/334xx/328xx devices bootloader 23.1 bootloader configuration the stm32f303x4(6/8)/334xx/328xx bootloader is activated by applying pattern2 (described in table 2: bootloader activation patterns ). the following table shows the hardware resources used by this bootloader. table 50. stm32f303x4(6/8)/334xx/328xx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 60 mhz with hsi 8 mhz as clock source. ram - 6 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 8 kbytes starting from address 0x1fffd800, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized the usart2 configuration is: 8-bits, even parity and 1 stop bit usart2_rx pin input pa3 pin: usart2 in reception mode usart2_tx pin output pa2 pin: usart2 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111111x (where x = 0 for write and x = 1 for read) i2c1_scl pin input/output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/output pb7 pin: data line is used in open-drain mode. docid13801 rev 21 99/155 AN2606 stm32f303x4(6/8)/334xx/328xx devices bootloader 154 the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. 23.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 30. bootloader selection for stm32f303x4(6/8)/334xx/328xx 23.3 bootloader version the following table lists the stm32f303x4(6/8)/334xx/328xx devices bootloader versions: 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n [ ) u h f h l y h g r q 8 6 $ 5 7 b [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ & r q i l j x u h , & [ ( [ h f x w h % / b , & b / r r s i r u , & [ 1 r 1 r < h v , & $ g g u h v v g h w h f w h g ? ? ]?o oo ]v? ???? ?}? ? table 51. stm32f303x4(6/8)/334xx/328xx bootloader versions bootloader version number description known limitations v5.0 initial bootloader version none stm32f401xb(c) devices bootloader AN2606 100/155 docid13801 rev 21 24 stm32f401xb(c) devices bootloader 24.1 bootloader configuration the stm32f401xb(c) bootloader is activated by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 52. stm32f401xb(c) configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 60 mhz using the pll. the hsi clock source is used at startup (interface detection phase) and when usart or spi or i2c interfaces are selected (once dfu bootloader is selected, the clock source will be derived from the external crystal). hse enabled the system clock frequency is 60 mhz. the hse clock source is used only when the dfu (usb fs device) interfaces are selected. the external clock must provide a frequency multiple of 1 mhz and ranging from 4 mhz to 26 mhz. - the clock security system (css) interrupt is enabled for the can and dfu bootloaders. any failure (or removal) of the external clock gene rates system reset. ram - 12 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 30424 bytes starting from address 0x1fff0000, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - voltage range is set to [1.62 v, 2.1 v]. in this range internal flash write operations are allowed only in byte format (half-word, word and double-word operations are not allowed). the voltage range can be configured in run time using bootloader commands. docid13801 rev 21 101/155 AN2606 stm32f401xb(c) devices bootloader 154 usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized the usart2 configuration is: 8-bits, even parity and 1 stop bit usart2_rx pin input pd6 pin: usart2 in reception mode usart2_tx pin output pd5 pin: usart2 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111001x (where x = 0 for write and x = 1 for read) i2c1_scl pin input/output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/output pb7 pin: data line is used in open-drain mode. i2c2 bootloader i2c2 enabled the i2c2 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111001x (where x = 0 for write and x = 1 for read) i2c2_scl pin input/output pb10 pin: clock line is used in open-drain mode. i2c2_sda pin input/output pb3 pin: data line is used in open-drain mode. i2c3 bootloader i2c3 enabled the i2c3 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111001x (where x = 0 for write and x = 1 for read) i2c3_scl pin input/output pa8 pin: clock line is used in open-drain mode. i2c3_sda pin input/output pb4 pin: data line is used in open-drain mode. table 52. stm32f401xb(c) configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32f401xb(c) devices bootloader AN2606 102/155 docid13801 rev 21 spi1 bootloader spi1 enabled the spi1 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi1_mosi pin input pa7 pin: slave data input line, used in push-pull pull-down mode spi1_miso pin output pa6 pin: slave data output line, used in push-pull pull-down mode spi1_sck pin input pa5 pin: slave clock line, used in push-pull pull-down mode spi1_nss pin input pa4 pin: slave chip select pin used in push-pull pull-down mode. spi2 bootloader spi2 enabled the spi2 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi2_mosi pin input pb15 pin: slave data input line, used in push-pull pull-down mode spi2_miso pin output pb14 pin: slave data output line, used in push-pull pull-down mode spi2_sck pin input pb13 pin: slave clock line, used in push- pull pull-down mode spi2_nss pin input pb12 pin: slave chip select pin used in push-pull pull-down mode. spi3 bootloader spi3 enabled the spi3 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi3_mosi pin input pc12 pin: slave data input line, used in push-pull pull-down mode spi3_miso pin output pc11 pin: slave data output line, used in push-pull pull-down mode spi3_sck pin input pc10 pin: slave clock line, used in push- pull pull-down mode spi3_nss pin input pa15 pin: slave chip select pin used in push-pull pull-down mode. table 52. stm32f401xb(c) configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 103/155 AN2606 stm32f401xb(c) devices bootloader 154 the system clock is derived from the embedded internal high-speed rc for usartx, i2cx and spix bootloaders. this internal clock is also used for can and dfu (usb fs device) but only for the selection phase. an external clock multiple of 1 mhz (between 4 and 26 mhz) is required for can and dfu bootloader execution after the selection phase. dfu bootloader usb enabled usb otg fs configured in forced device mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line no external pull-up resistor is required tim11 enabled this timer is used to determine the value of the hse. once the hse frequency is determined, the system clock is configured to 60 mhz using pll and hse. table 52. stm32f401xb(c) configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32f401xb(c) devices bootloader AN2606 104/155 docid13801 rev 21 24.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 31. bootloader selection for stm32f401xb(c) 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v q r < h v * h q h u d w h 6 \ v w h p u h v h w & r q i l j x u h 8 6 % 2 7 * ) 6 g h y l f h 8 6 % f d e o h ' h w h f w h g [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v + 6 ( g h w h f w h g \ h v q r , & [ $ g g u h v v ' h w h f w h g ( [ h f x w h % / b , & b / r r s i r u , & [ v} v} ? ? & r q i l j x u h , & [ & r q i l j x u h 6 3 , [ ' l v d e o h d o o l q w h u u x s w v r x u f h v 6 3 , [ g h w h f w v 6 \ q f k u r p h f k d q l v p v} ( [ h f x w h % / b 6 3 , b / r r s i r u 6 3 , [ ? ? ' l v d e o h d o o l q w h u u x s w v r x u f h v docid13801 rev 21 105/155 AN2606 stm32f401xb(c) devices bootloader 154 24.3 bootloader version the following table lists the stm32f401xb(c) devices bootloader version. table 53. stm32f401xb(c) bootloader versions bootloader version number description known limitations v13.0 initial bootloader version none stm32f401xd(e) devices bootloader AN2606 106/155 docid13801 rev 21 25 stm32f401xd(e) devices bootloader 25.1 bootloader configuration the stm32f401xd(e) bootloader is activated by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 54. stm32f401xd(e) configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 60 mhz using the pll. the hsi clock source is used at startup (interface detection phase) and when usart or spi or i2c interfaces are selected (once dfu bootloader is selected, the clock source will be derived from the external crystal). hse enabled the system clock frequency is 60 mhz. the hse clock source is used only when the dfu (usb fs device) interfaces are selected. the external clock must provide a frequency multiple of 1 mhz and ranging from 4 mhz to 26 mhz. - the clock security system (css) interrupt is enabled for the can and dfu bootloaders. any failure (or removal) of the external clock gene rates system reset. ram - 12 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 30424 bytes starting from address 0x1fff0000, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - voltage range is set to [1.62 v, 2.1 v]. in this range internal flash write operations are allowed only in byte format (half-word, word and double-word operations are not allowed). the voltage range can be configured in run time using bootloader commands. docid13801 rev 21 107/155 AN2606 stm32f401xd(e) devices bootloader 154 usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized the usart2 configuration is: 8-bits, even parity and 1 stop bit usart2_rx pin input pd6 pin: usart2 in reception mode usart2_tx pin output pd5 pin: usart2 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111001x (where x = 0 for write and x = 1 for read) i2c1_scl pin input/output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/output pb7 pin: data line is used in open-drain mode. i2c2 bootloader i2c2 enabled the i2c2 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111001x (where x = 0 for write and x = 1 for read) i2c2_scl pin input/output pb10 pin: clock line is used in open-drain mode. i2c2_sda pin input/output pb3 pin: data line is used in open-drain mode. i2c3 bootloader i2c3 enabled the i2c3 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111001x (where x = 0 for write and x = 1 for read) i2c3_scl pin input/output pa8 pin: clock line is used in open-drain mode. i2c3_sda pin input/output pb4 pin: data line is used in open-drain mode. table 54. stm32f401xd(e) configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32f401xd(e) devices bootloader AN2606 108/155 docid13801 rev 21 spi1 bootloader spi1 enabled the spi1 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi1_mosi pin input pa7 pin: slave data input line, used in push-pull pull-down mode spi1_miso pin output pa6 pin: slave data output line, used in push-pull pull-down mode spi1_sck pin input pa5 pin: slave clock line, used in push-pull pull-down mode spi1_nss pin input pa4 pin: slave chip select pin used in push-pull pull-down mode. spi2 bootloader spi2 enabled the spi2 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi2_mosi pin input pb15 pin: slave data input line, used in push-pull pull-down mode spi2_miso pin output pb14 pin: slave data output line, used in push-pull pull-down mode spi2_sck pin input pb13 pin: slave clock line, used in push- pull pull-down mode spi2_nss pin input pb12 pin: slave chip select pin used in push-pull pull-down mode. spi3 bootloader spi3 enabled the spi3 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi3_mosi pin input pc12 pin: slave data input line, used in push-pull pull-down mode spi3_miso pin output pc11 pin: slave data output line, used in push-pull pull-down mode spi3_sck pin input pc10 pin: slave clock line, used in push- pull pull-down mode spi3_nss pin input pa15 pin: slave chip select pin used in push-pull pull-down mode. table 54. stm32f401xd(e) configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 109/155 AN2606 stm32f401xd(e) devices bootloader 154 the system clock is derived from the embedded internal high-speed rc for usartx, i2cx and spix bootloaders. this internal clock is also used for can and dfu (usb fs device) but only for the selection phase. an external clock multiple of 1 mhz (between 4 and 26 mhz) is required for can and dfu bootloader execution after the selection phase. dfu bootloader usb enabled usb otg fs configured in forced device mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line no external pull-up resistor is required tim11 enabled this timer is used to determine the value of the hse. once the hse frequency is determined, the system clock is configured to 60 mhz using pll and hse. table 54. stm32f401xd(e) configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32f401xd(e) devices bootloader AN2606 110/155 docid13801 rev 21 25.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 32. bootloader selection for stm32f401xd(e) 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v q r < h v * h q h u d w h 6 \ v w h p u h v h w & r q i l j x u h 8 6 % 2 7 * ) 6 g h y l f h 8 6 % f d e o h ' h w h f w h g [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v + 6 ( g h w h f w h g \ h v q r , & [ $ g g u h v v ' h w h f w h g ( [ h f x w h % / b , & b / r r s i r u , & [ v} v} ? ? & r q i l j x u h , & [ & r q i l j x u h 6 3 , [ ' l v d e o h d o o l q w h u u x s w v r x u f h v 6 3 , [ g h w h f w v 6 \ q f k u r p h f k d q l v p v} ( [ h f x w h % / b 6 3 , b / r r s i r u 6 3 , [ ? ? ' l v d e o h d o o l q w h u u x s w v r x u f h v docid13801 rev 21 111/155 AN2606 stm32f401xd(e) devices bootloader 154 25.3 bootloader version the following table lists the stm32f401xd(e) devices bootloader version. table 55. stm32f401xd(e) bootloader versions bootloader version number description known limitations v13.1 initial bootloader version none stm32f411xx devices bootloader AN2606 112/155 docid13801 rev 21 26 stm32f411xx devices bootloader 26.1 bootloader configuration the stm32f411xx bootloader is activated by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 56. stm32f411xx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 60 mhz using the pll. the hsi clock source is used at startup (interface detection phase) and when usart or spi or i2c interfaces are selected (once dfu bootloader is selected, the clock source will be derived from the external crystal). hse enabled the system clock frequency is 60 mhz. the hse clock source is used only when the dfu (usb fs device) interfaces are selected. the external clock must provide a fre- quency multiple of 1 mhz and ranging from 4 mhz to 26 mhz. - the clock security system (css) interrupt is enabled for the can and dfu bootload- ers. any failure (or removal) of the external clock generates system reset. ram - 12 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 30424 bytes starting from address 0x1fff0000, contain the bootloader firm- ware iwdg - the independent watchdog (iwdg) pres- caler is configured to its maximum value. it is periodically refreshed to prevent watch- dog reset (in case the hardware iwdg option was previously enabled by the user). power - voltage range is set to [1.62 v, 2.1 v]. in this range internal flash write operations are allowed only in byte format (half-word, word and double-word operations are not allowed). the voltage range can be config- ured in run time using bootloader com- mands. docid13801 rev 21 113/155 AN2606 stm32f411xx devices bootloader 154 usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized the usart2 configuration is: 8-bits, even parity and 1 stop bit usart2_rx pin input pd6 pin: usart2 in reception mode usart2_tx pin output pd5 pin: usart2 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111001x (where x = 0 for write and x = 1 for read) i2c1_scl pin input/output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/output pb7 pin: data line is used in open-drain mode. i2c2 bootloader i2c2 enabled the i2c2 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111001x (where x = 0 for write and x = 1 for read) i2c2_scl pin input/output pb10 pin: clock line is used in open-drain mode. i2c2_sda pin input/output pb3 pin: data line is used in open-drain mode. i2c3 bootloader i2c3 enabled the i2c3 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111001x (where x = 0 for write and x = 1 for read) i2c3_scl pin input/output pa8 pin: clock line is used in open-drain mode. i2c3_sda pin input/output pb4 pin: data line is used in open-drain mode. table 56. stm32f411xx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32f411xx devices bootloader AN2606 114/155 docid13801 rev 21 spi1 bootloader spi1 enabled the spi1 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi1_mosi pin input pa7 pin: slave data input line, used in push-pull pull-down mode spi1_miso pin output pa6 pin: slave data output line, used in push-pull pull-down mode spi1_sck pin input pa5 pin: slave clock line, used in push-pull pull-down mode spi1_nss pin input pa4 pin: slave chip select pin used in push-pull pull-down mode. spi2 bootloader spi2 enabled the spi2 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi2_mosi pin input pb15 pin: slave data input line, used in push-pull pull-down mode spi2_miso pin output pb14 pin: slave data output line, used in push-pull pull-down mode spi2_sck pin input pb13 pin: slave clock line, used in push- pull pull-down mode spi2_nss pin input pb12 pin: slave chip select pin used in push-pull pull-down mode. spi3 bootloader spi3 enabled the spi3 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi3_mosi pin input pc12 pin: slave data input line, used in push-pull pull-down mode spi3_miso pin output pc11 pin: slave data output line, used in push-pull pull-down mode spi3_sck pin input pc10 pin: slave clock line, used in push- pull pull-down mode spi3_nss pin input pa15 pin: slave chip select pin used in push-pull pull-down mode. table 56. stm32f411xx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 115/155 AN2606 stm32f411xx devices bootloader 154 the system clock is derived from the embedded internal high-speed rc for usartx, i2cx and spix bootloaders. this internal clock is also used for can and dfu (usb fs device) but only for the selection phase. an external clock multiple of 1 mhz (between 4 and 26 mhz) is required for can and dfu bootloader execution after the selection phase. dfu bootloader usb enabled usb otg fs configured in forced device mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line no external pull-up resistor is required tim11 enabled this timer is used to determine the value of the hse. once the hse frequency is determined, the system clock is configured to 60 mhz using pll and hse. table 56. stm32f411xx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32f411xx devices bootloader AN2606 116/155 docid13801 rev 21 26.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 33. bootloader se lection for stm32f411xx 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v q r < h v * h q h u d w h 6 \ v w h p u h v h w & r q i l j x u h 8 6 % 2 7 * ) 6 g h y l f h 8 6 % f d e o h ' h w h f w h g [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v + 6 ( g h w h f w h g \ h v q r , & [ $ g g u h v v ' h w h f w h g ( [ h f x w h % / b , & b / r r s i r u , & [ v} v} ? ? & r q i l j x u h , & [ & r q i l j x u h 6 3 , [ ' l v d e o h d o o l q w h u u x s w v r x u f h v 6 3 , [ g h w h f w v 6 \ q f k u r p h f k d q l v p v} ( [ h f x w h % / b 6 3 , b / r r s i r u 6 3 , [ ? ? ' l v d e o h d o o l q w h u u x s w v r x u f h v docid13801 rev 21 117/155 AN2606 stm32f411xx devices bootloader 154 26.3 bootloader version the following table lists the stm32f411xx devices bootloader version. table 57. stm32f411xx bootloader versions bootloader version number description known limitations v13.0 initial bootloader version none stm32l1xxx6(8/b)a devices bootloader AN2606 118/155 docid13801 rev 21 27 stm32l1xxx6(8/b)a devices bootloader 27.1 bootloader configuration the stm32l1xxx6(8/b)a bootloader is activated by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. table 58. stm32l1xxx6(8/b)a configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 16 mhz. ram - 2 kbytes starting from address 0x20000000 are used by the bootloader firmware. system memory - 4 kbytes starting from address 0x1ff00000 contain the bootloader firmware. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - voltage range is set to voltage range 1. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized, the usart2 configuration is: 8 bits, even parity and 1 stop bit. usart2_rx pin input pd6 pin: usart2 in reception mode usart2_tx pin output pd5 pin: usart2 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host. docid13801 rev 21 119/155 AN2606 stm32l1xxx6(8/b)a devices bootloader 154 27.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 34. bootloader selection for stm32l1xxx6(8/b)a devices 27.3 bootloader version the following table lists the stm32l1xxx6(8/b)a devices bootloader versions: 0 6 9 6 \ v w h p 5 h v h w [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ q r < h v 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n ' l v d e o h d o o l q w h u u x s w v r x u f h v table 59. stm32l1xxx6(8/b)a bootloader versions bootloader version number description known limitations v2.0 initial bootloader version when a read memory co mmand or write memory command is issued with an unsupported memory address and a correct address checksum (ie. address 0x6000 0000), the command is aborted by the bootloader device, but the nack (0x1f) is not sent to the host. as a result, the next 2 bytes (which are the number of bytes to be read/written and its checksum) are considered as a new command and its checksum. (1) 1. if the ?number of data - 1? (n-1) to be read/written is not equal to a valid command code, then the limitation is not perceived from the host since the command is nacked anyway (as an unsupported new command). stm32l1xxxe devices bootloader AN2606 120/155 docid13801 rev 21 28 stm32l1xxxe devices bootloader 28.1 bootloader configuration the stm32l1xxxe bootloader is activated by applying pattern4 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 60. stm32l1xxxe configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 16 mhz using the hsi. this is used only for usart1 and usart2 bootloaders and during usb detection for dfu bootloader (once the dfu bootloader is selected, the clock source will be derived from the external crystal). hse enabled the external clock is mandatory only for dfu bootloader and it must be in the following range: [24, 16, 12, 8, 6, 4, 3, 2] mhz. the pll is used to generate the usb 48 mhz clock and the 32 mhz clock for the system clock. - the clock security system (css) interrupt is enabled for the dfu bootloader. any failure (or removal) of the external clock generates system reset. iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power voltage range is set to voltage range 1. system memory - 8 kbytes starting from address 0x1ff0 0000. this area contains the bootloader firmware. ram - 4 kbytes starting from address 0x20000000 are used by the bootloader firmware. usart1 bootloader usart1 enabled once initialized, the usart1 configuration is: 8 bits, even parity and 1 stop bit. usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloader. docid13801 rev 21 121/155 AN2606 stm32l1xxxe devices bootloader 154 the system clock is derived from the embedded internal high-speed rc for usartx bootloader. this internal clock is used also for dfu bootloader but only for the selection phase. an external clock in the range of [24, 16, 12, 8, 6, 4, 3, 2] mhz is required for dfu bootloader execution after the selection phase. usart2 bootloader usart2 enabled once initialized, the usart2 configuration is: 8 bits, even parity and 1 stop bit. the usart2 uses its remapped pins. usart2_rx pin input pd6 pin: usart2 in reception mode usart2_tx pin output pd5 pin: usart2 in transmission mode dfu bootloader usb enabled usb used in fs mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line an external pull-up re sistor 1.5 kohm must be connected to usb_dp pin. table 60. stm32l1xxxe configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32l1xxxe devices bootloader AN2606 122/155 docid13801 rev 21 28.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 35. bootloader select ion for stm32l1xxxe devices 0 6 9 6 \ v w h p 5 h v h w & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ q r q r & ? ]? ? ? ? ~ & ? a /( so ???e ]? ]?z]v ]v?x ^ z d ? ?? /( so ??? ]? ]?z]v ]v?x ^ z d ? ?? 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n & r q w l q x h % r r w o r d g h u h [ h f x w l r q v} ? ? v} v} ' l v d e o h d o o l q w h u u x s w v r x u f h v v} - x p s w r x v h u f r g h l q % d q n :u? ?} ? ? } ]v vl ? ? ? ? /( so ???e ]? ]?z]v ]v?x ^ z d ? ?? /( so ??? ]? ]?z]v ]v?x ^ z d ? ?? v} v} - x p s w r x v h u f r g h l q % d q n :u? ?} ? ? } ]v vl ? ? ? ? w?}? ?]}v o o? vo ? ? w h o}l ~zo? 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v < h v + 6 ( g h w h f w h g ? ? * h q h u d w h 6 \ v w h p u h v h w v} & r q i l j x u h 8 6 % [ ) u h f h l y h g r q 8 6 $ 5 7 [ 8 6 % f d e o h ' h w h f w h g < h v docid13801 rev 21 123/155 AN2606 stm32l1xxxe devices bootloader 154 28.3 bootloader version the following table lists the stm32l1xxxe devices bootloader versions: table 61. stm32l1xxxe bootloader versions bootloader version number description known limitations v4.0 initial bootloader version ? for the usart interface, two consecutive nacks (instead of 1 nack) are sent when a read memory or write memory command is sent and the rdp level is active. stm32l05xxx/06xxx devices bootloader AN2606 124/155 docid13801 rev 21 29 stm32l05xxx/06xxx devices bootloader 29.1 bootloader configuration the stm32l05xxx/06xxx bootloader is activated by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 62. stm32l05xxx/06xxx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the system clock frequency is 32 mhz with hsi 16 mhz as clock source. power - voltage range is set to voltage range 1. ram - 4 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 4 kbytes starting from address 0x1ff00000, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized the usart2 configuration is: 8-bits, even parity and 1 stop bit usart2_rx pin input pa3 pin: usart2 in reception mode usart2_tx pin output pa2 pin: usart2 in transmission mode usart1 and usart2 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. docid13801 rev 21 125/155 AN2606 stm32l05xxx/06xxx devices bootloader 154 the system clock is derived from the embedded internal high-speed rc for all bootloader interfaces. no external quartz is required for bootloader operations. spi1 bootloader spi1 enabled the spi1 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi1_mosi pin input pa7 pin: slave data input line, used in push-pull pull-down mode spi1_miso pin output pa6 pin: slave data output line, used in push-pull pull-down mode spi1_sck pin input pa5 pin: slave clock line, used in push-pull pull-down mode spi1_nss pin input pa4 pin: slave chip select pin used in push-pull pull-down mode. spi2 bootloader spi2 enabled the spi2 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi2_mosi pin input pb15 pin: slave data input line, used in push-pull pull-down mode spi2_miso pin output pb14 pin: slave data output line, used in push-pull pull-down mode spi2_sck pin input pb13 pin: slave clock line, used in push- pull pull-down mode spi2_nss pin input pb12 pin: slave chip select pin used in push-pull pull-down mode. table 62. stm32l05xxx/06xxx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32l05xxx/06xxx devices bootloader AN2606 126/155 docid13801 rev 21 29.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 36. bootloader selection for stm32l05xxx/06xxx 29.3 bootloader version the following table lists the stm32l05xxx/06xxx devices bootloader versions: 0 6 9 6 \ v w h p 5 h v h w 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n q r [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ]?o oo }?z ? ]v? ?( ? o}l? \ h v v} & r q i l j x u h 6 3 , [ 6 3 , [ g h w h f w v 6 \ q f k u r p h f k d q l v p ( [ h f x w h % / b 6 3 , b / r r s i r u 6 3 , [ ? ? ]?o oo }?z ? ]v? ?( ? o}l? ' l v d e o h d o o l q w h u u x s w v r x u f h v table 63. stm32l05xxx/06xxx bootloader versions bootloader version number description known limitations v12.0 initial bootloader version none docid13801 rev 21 127/155 AN2606 stm32l476xx/486xx devices bootloader 154 30 stm32l476xx/486xx devices bootloader 30.1 bootloader configuration the stm32l476xx/486xx bootloader is acti vated by applying pattern5 (described in table 2: bootloader activation patterns ). the following table shows the hardware resources used by this bootloader. table 64.stm32l476xx/486xx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the hsi is used at startup as clock source for system clock configured to 72 mhz and for usart and i2c bootloader operation. hse enabled the hse is used only when the usb interface is selected and the lse is not present. the hse must have one of the following value [24,20, 18,16,12,9,8,6,4] mhz. lse enabled the lse is used to trim the msi which is configured to 48 mhz as usb clock source. the lse must be equal to 32,768 khz. if the lse is not detected, the hse will be used instead if usb is connected. msi enabled the msi is configured to 48 mhz and will be used as usb clock source. the msi is used only if lse is detected, otherwise, hse will be used if usb is connected. - the clock security system (css) interrupt is enabled when lse or hse is enabled. any failure (or remova l) of the external clock generates system reset. ram - 12 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 28672 bytes starting from address 0x1fff0000, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - the dfu can?t be used to communicate with bootloader if the voltage scaling range 2 is selected. bootloader firmware doesn?t configure voltage scaling range value in pwr_cr1 register. stm32l476xx/486xx devices bootloader AN2606 128/155 docid13801 rev 21 usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart2 bootloader usart2 enabled once initialized the usart2 configuration is: 8-bits, even parity and 1 stop bit usart2_rx pin input pa3 pin: usart2 in reception mode usart2_tx pin output pa2 pin: usart2 in transmission mode usart3 bootloader usart3 enabled once initialized the usart3 configuration is: 8-bits, even parity and 1 stop bit usart3_rx pin input pc11 pin: usart3 in reception mode usart3_tx pin output pc10 pin: usart3 in transmission mode usartx bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b1000011x (where x = 0 for write and x = 1 for read) i2c1_scl pin input/output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/output pb7 pin: data line is used in open-drain mode. i2c2 bootloader i2c2 enabled the i2c2 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b1000011x (where x = 0 for write and x = 1 for read) i2c2_scl pin input/output pb10 pin: clock line is used in open-drain mode. i2c2_sda pin input/output pb11 pin: data line is used in open-drain mode. i2c3 bootloader i2c3 enabled the i2c3 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address is 0b1000011x (where x = 0 for write and x = 1 for read) i2c3_scl pin input/output pc0 pin: clock line is used in open-drain mode. i2c3_sda pin input/output pc1 pin: data line is used in open-drain mode. table 64.stm32l476xx/486xx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 129/155 AN2606 stm32l476xx/486xx devices bootloader 154 for usartx and i2cx bootloaders no external clock is required. usb bootloader (dfu) requires either an lse (low-speed external clock) or a hse (high- speed external clock) : ? in case, the lse is present regardless t he hse presence, the msi will be configured and trimmed by the lse to provide an accurate clock equal to 48 mhz which is the clock source of the usb. the system cloc k is kept clocked to 24 mhz by the hsi. ? in case, the hse is present, the system clock and usb clock will be configured respectively to 24 mhz and 48 mhz with hse as clock source. dfu bootloader usb enabled usb otg fs configured in forced device mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line no external pull-up resistor is required tim17 enabled this timer is used to determine the value of the hse. once the hse frequency is determined, the system clock is configured to 72 mhz using pll and hse. table 64.stm32l476xx/486xx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32l476xx/486xx devices bootloader AN2606 130/155 docid13801 rev 21 30.2 bootloader selection the figures below show the bootloader selection mechanism. figure 37. dual bank boot implementation for stm32l476xx/486xx bootloader v10.x 6 \ v w h p 5 h v h w /( }}? a v} ? ? 3 u r w h f w l r q o h y h o h q d e o h g & r q w l q x h % r r w o r d g h u h [ h f x w l r q v} , i 9 d o x h r i i l u v w d g g u h v v r i % d q n l v z l w k l q l q w 6 5 $ 0 d g g u h v v ^ ? vl ^? ?} vl? ^ ? vl ^? ?} vl ? ? v} :u? ?} ? ? } ]v vl? :u? ?} ? ? } ]v vl ? ? , i 9 d o x h r i i l u v w d g g u h v v r i % d q n l v z l w k l q l q w 6 5 $ 0 d g g u h v v ^ ? vl ^? ?} vl? ^ ? vl ^? ?} vl ? ? :u? ?} ? ? } ]v vl? :u? ?} ? ? } ]v vl 3 u r w h f w l r q o h y h o h q d e o h g , i 9 d o x h r i i l u v w d g g u h v v r i % d q n l v z l w k l q l q w 6 5 $ 0 d g g u h v v ? ? v} v} & r q w l q x h % r r w o r d g h u h [ h f x w l r q v} ? ? 0 6 y 9 docid13801 rev 21 131/155 AN2606 stm32l476xx/486xx devices bootloader 154 figure 38.bootloader v10.x sele ction for stm32l476xx/486xx % r r w o r d g h u 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ]?z , ^ ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v 1 r < h v * h q h u d w h 6 \ v w h p u h v h w & r q i l j x u h 8 6 % 2 7 * ) 6 g h y l f h 8 6 % f d e o h ' h w h f w h g [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ' l v d e o h d o o l q w h u u x s w v r x u f h v < h v + 6 ( g h w h f w h g < h v 1 r e} , & $ g g u h v v ' h w h f w h g ( [ h f x w h % / b , & b / r r s i r u , & [ z ? 1 r & r q i l j x u h d o o , & v & r q i l j x u h 8 6 % f o r f n w r 0 + ] z l w k 0 6 , d v f o r f n v r x u f h ' l v d e o h d o o l q w h u u x s w v r x u f h v / 6 ( g h w h f w h g 1 r & r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] z l w k + 6 , < h v & r q i l j x u h 8 6 % f o r f n w r 0 + ] z l w k + 6 , d v f o r f n v r x u f h 0 6 , x v h g d v 8 6 % f o r f n v r x u f h < h v e} 0 6 y 9 stm32l476xx/486xx devices bootloader AN2606 132/155 docid13801 rev 21 30.3 bootloader version the following table lists the stm32l476xx/486 xx devices bootloader v10.x versions: table 65.stm32l476xx/486xx bootloader v10.x versions bootloader version number description known limitations v10.0 deprecated version (not used) none v10.1 initial bootloader version write in sram is corrupted v10.2 fix write in sram issue none v10.3 add support of msi as usb clock source (msi is trimmed by lse). update dual bank boot feature to support the case when user stack is mapped in sram2. none docid13801 rev 21 133/155 AN2606 stm32f446xx devices bootloader 154 31 stm32f446xx devices bootloader 31.1 bootloader configuration the stm32f446xx bootloader is activated by applying pattern1 (described in table 2: bootloader activation patterns ). the following table shows th e hardware resources used by this bootloader. table 66.stm32f446xx configuration in system memory boot mode bootloader feature/peripheral state comment common to all bootloaders rcc hsi enabled the hsi is used at startup as clock source for system clock configured to 60 mhz and for usart, i2c and spi bootloader operation. hse enabled the hse is used only when the can or the dfu (usb fs device) interfaces are selected. in this ca se the system clock configured to 60 mhz with hse as clock source. the hse frequency must be multiple of 1 mhz and ranging from 4 mhz to 26 mhz. - the clock security system (css) interrupt is enabled for the can and dfu bootloaders. any failure (or removal) of the external clock generates system reset. ram - 12 kbytes starting from address 0x20000000 are used by the bootloader firmware system memory - 30424 bytes starting from address 0x1fff0000, contain the bootloader firmware iwdg - the independent watchdog (iwdg) prescaler is configured to its maximum value. it is periodically refreshed to prevent watchdog reset (in case the hardware iwdg option was previously enabled by the user). power - the voltage range is [1.71 v, 3.6 v]. in this range: - flash wait states 3. - system clock 60 mhz. - prefetch disabled. - flash write operation by byte (refer to section bootloader memory management for more information). stm32f446xx devices bootloader AN2606 134/155 docid13801 rev 21 usart1 bootloader usart1 enabled once initialized the usart1 configuration is: 8-bits, even parity and 1 stop bit usart1_rx pin input pa10 pin: usart1 in reception mode usart1_tx pin output pa9 pin: usart1 in transmission mode usart3 bootloader (on pb10/pb11) usart3 enabled once initialized the usart3 configuration is: 8-bits, even parity and 1 stop bit usart3_rx pin input pb11 pin: usart3 in reception mode usart3_tx pin output pb10 pin: usart3 in transmission mode usart3 bootloader (on pc10/pc11) usart3 enabled once initialized the usart3 configuration is: 8-bits, even parity and 1 stop bit usart3_rx pin input pc11 pin: usart3 in reception mode usart3_tx pin output pc10 pin: usart3 in transmission mode usart1 and usart3 bootloaders systick timer enabled used to automatically detect the serial baud rate from the host for usartx bootloaders. can2 bootloader can2 enabled once initialized the ca n2 configuration is: baudrate 125 kbps, 11-bit identifier. note: can1 is clocked during can2 bootloader execution because in can1 manages the communication between can2 and sram. can2_rx pin input pb5 pin: can2 in reception mode can2_tx pin output pb13 pin: can2 in transmission mode i2c1 bootloader i2c1 enabled the i2c1 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111100x (where x = 0 for write and x = 1 for read) i2c1_scl pin input/output pb6 pin: clock line is used in open-drain mode. i2c1_sda pin input/output pb9 pin: data line is used in open-drain mode. i2c2 bootloader i2c2 enabled the i2c2 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111100x (where x = 0 for write and x = 1 for read) i2c2_scl pin input/output pf1 pin: clock line is used in open-drain mode. i2c2_sda pin input/output pf0 pin: data line is used in open-drain mode. table 66.stm32f446xx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 135/155 AN2606 stm32f446xx devices bootloader 154 i2c3 bootloader i2c3 enabled the i2c3 configuration is: i2c speed: up to 400 khz, 7-bit address, slave mode, analog filter on. slave 7-bit address: 0b0111100x (where x = 0 for write and x = 1 for read) i2c3_scl pin input/output pa8 pin: clock line is used in open-drain mode. i2c3_sda pin input/output pc9 pin: data line is used in open-drain mode. spi1 bootloader spi1 enabled the spi1 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi1_mosi pin input pa7 pin: slave data input line, used in push-pull pull-down mode spi1_miso pin output pa6 pin: slave data output line, used in push-pull pull-down mode spi1_sck pin input pa5 pin: slave clock line, used in push-pull pull-down mode spi1_nss pin input pa4 pin: slave chip select pin used in push-pull pull-up mode. spi2 bootloader spi2 enabled the spi2 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi2_mosi pin input pb15 pin: slave data input line, used in push-pull pull-down mode spi2_miso pin output pb14 pin: slave data output line, used in push-pull pull-down mode spi2_sck pin input pc7 pin: slave clock line, used in push-pull pull-down mode spi2_nss pin input pb12 pin: slave chip select pin used in push-pull pull-up mode. table 66.stm32f446xx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment stm32f446xx devices bootloader AN2606 136/155 docid13801 rev 21 the system clock is derived from the embed ded internal high-speed rc for usartx and i2cx bootloaders. this internal clock is also used for can and dfu (usb fs device) but only for the selection phase. an external clock multiple of 1 mhz (between 4 and 26 mhz) is required for can and dfu bootloader execution after the selection phase. spi4 bootloader spi4 enabled the spi4 configuration is: slave mode, full duplex, 8-bit msb, speed up to 8 mhz, polarity: cpol low, cpha low, nss hardware. spi4_mosi pin input pe14 pin: slave data input line, used in push-pull pull-down mode spi4_miso pin output pe13 pin: slave data output line, used in push-pull pull-down mode spi4_sck pin input pe12 pin: slave clock line, used in push- pull pull-down mode spi4_nss pin input pe11 pin: slave chip select pin used in push-pull pull-up mode. dfu bootloader usb enabled usb otg fs configured in forced device mode usb_dm pin input/output pa11: usb dm line. usb_dp pin pa12: usb dp line no external pull-up resistor is required can2 and dfu bootloaders tim17 enabled this timer is used to determine the value of the hse. once the hse frequency is determinated, the system clock is configured to 60 mhz using pll and hse. table 66.stm32f446xx configuration in system memory boot mode (continued) bootloader feature/peripheral state comment docid13801 rev 21 137/155 AN2606 stm32f446xx devices bootloader 154 31.2 bootloader selection the figure below shows the bootloader selection mechanism. figure 39.bootloader v9.x selection for stm32f446xx ^??? u z ? ? 6 \ v w h p , q l w & o r f n * 3 , 2 v , : ' * 6 \ v 7 l f n 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] d q g 8 6 % f o r f n w r 0 + ] ( [ h f x w h ' ) 8 e r r w o r d g h u x v l q j 8 6 % l q w h u u x s w v 1 r < h v * h q h u d w h 6 \ v w h p u h v h w & r q i l j x u h 8 6 % 2 7 * ) 6 g h y l f h ) u d p h g h w h f w h g r q & $ 1 [ 1 r + 6 ( g h w h f w h g ( [ h f x w h % / b & $ 1 b / r r s i r u & $ 1 8 6 % f d e o h ' h w h f w h g [ ) u h f h l y h g r q 8 6 $ 5 7 [ & r q i l j x u h 8 6 $ 5 7 [ ( [ h f x w h % / b 8 6 $ 5 7 b / r r s i r u 8 6 $ 5 7 [ ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v 1 r & r q i l j x u h & $ 1 + 6 ( g h w h f w h g ' l v d e o h d o o l q w h u u x s w v r x u f h v \ h v \ h v \ h v 1 r 1 r 5 h f r q i l j x u h 6 \ v w h p f o r f n w r 0 + ] e} & r q i l j x u h , & [ , & $ g g u h v v ' h w h f w h g ( [ h f x w h % / b , & b / r r s i r u , & [ z ? ' l v d e o h d o o l q w h u u x s w v r x u f h v 1 r 6 \ q f k u r p h f k d q l v p g h w h f w h g r q 6 3 , [ ( [ h f x w h % / b 6 3 , b / r r s i r u 6 3 , [ z ? ' l v d e o h d o o l q w h u u x s w v r x u f h v 0 6 y 9 stm32f446xx devices bootloader AN2606 138/155 docid13801 rev 21 31.3 bootloader version the following table lists the stm32f446xx devices bootloader v9.x versions: table 67.stm32f446xx bootloader v9.x versions bootloader version number description known limitations v9.0 initial bootloader version none docid13801 rev 21 139/155 AN2606 device-dependent bootloader parameters 154 32 device-dependent bootloader parameters the bootloader protocol?s command set and sequences for each serial peripheral are the same for all stm32 devices. however, some parameters depend on device and bootloader version: ? pid (product id) ? valid ram memory addresses (ram area used during bootloader execution is not accessible) accepted by the bootloader when the read memory, go and write memory commands are requested. ? system memory area. the table below shows the values of these parameters for each stm32 device bootloader in production. table 68. bootloader device-dependent parameters stm32 series device pid bl id ram memory system memory f0 stm32f05xxx and stm32f030x8 devices 0x440 0x21 0x20000800 - 0x20001fff 0x1fffec00 - 0x1ffff7ff stm32f03xxx 0x444 0x10 0x20000800 - 0x20000fff stm32f04xxx 0x445 0xa0 n.a 0x1fffc400 - 0x1ffff7ff stm32f07xxx 0x448 0xa1 0x20001800 - 0x20003fff 0x1fffc800 - 0x1ffff7ff f1 stm32f10xxx low-density 0x412 na 0x20000200 - 0x200027ff 0x1ffff000 - 0x1ffff7ff medium-density 0x410 na 0x20000200 - 0x20004fff high-density 0x414 na 0x20000200 - 0x2000ffff medium-density value line 0x420 0x10 0x20000200 - 0x20001fff high-density value line 0x428 0x10 0x20000200 - 0x20007fff stm32f105xx/107xx 0x418 na 0x20001000 - 0x2000ffff 0x1fffb000 - 0x1ffff7ff stm32f10xxx xl-density 0x430 0x21 0x20000800 - 0x20017fff 0x1fffe000 - 0x1ffff7ff f2 stm32f2xxxx 0x411 0x20 0x20002000 - 0x2001ffff 0x1fff0000 - 0x1fff77ff 0x33 f3 stm32f373xx 0x432 0x41 0x20001400 - 0x20007fff 0x1fffd800 - 0x1ffff7ff stm32f378xx 0x50 0x20001000 - 0x20007fff stm32f302xb(c)/303xb(c) 0x422 0x41 0x20001400 - 0x20009fff stm32f358xx 0x50 stm32f301xx/302x4(6/8) 0x439 0x40 0x20001800 - 0x20003fff stm32f318xx 0x50 stm32f303x4 (6/8)/334xx/328xx 0x438 0x50 0x20001800 - 0x20002fff device-dependent bootloader parameters AN2606 140/155 docid13801 rev 21 f4 stm32f40xxx/41xxx 0x413 0x31 0x20002000 - 0x2001ffff 0x1fff0000 - 0x1fff77ff 0x90 0x20003000 - 0x2001ffff stm32f42xxx/43xxx 0x419 0x70 0x20003000 - 0x2002ffff 0x90 stm32f401xb(c) 0x423 0xd1 0x20003000 - 0x2000ffff stm32f401xd(e) 0x433 0xd1 0x20003000 - 0x20017fff stm32f411xx 0x431 0xd0 0x20003000 - 0x2001ffff stm32f446xx 0x421 0x90 0x20003000 - 0x2001ffff l0 stm32l05xxx/06xxx 0x417 0xc0 0x20001000 - 0x20001fff 0x1ff00000 - 0x1ff00fff l1 stm32l1xxx6(8/b) 0x416 0x20 0x20000800 - 0x20003fff stm32l1xxx6(8/b)a 0x429 0x20 0x20001000 - 0x20007fff stm32l1xxxc 0x427 0x40 0x1ff00000 - 0x1ff01fff stm32l1xxxd 0x436 0x45 0x20001000 - 0x2000bfff stm32l1xxxe 0x437 0x40 0x20001000 - 0x20013fff l4 stm32l476xx/486xx 0x415 0xa3 0x20003000 - 0x20017fff 0x1fff0 000 - 0x1fff6fff table 68. bootloader device-dependent parameters (continued) stm32 series device pid bl id ram memory system memory docid13801 rev 21 141/155 AN2606 bootloader timing 154 33 bootloader timing this section presents the typical timings of the bootloader firmware that should be used to ensure correct synchronization between host and stm32 device. two types of timings will be described herein: ? stm32 device bootloader resources initialization duration. ? communication interface selection duration. after these timings the bootloader is re ady to receive and execute host commands. 33.1 bootloader startup timing after bootloader reset, the host should wait until the stm32 bootloader is ready to start detection phase with a specific interface communication. this time corresponds to bootloader startup timing, during which resources used by bootloader are initialized. figure 40. bootloader startup timing description the table below contains the minimum startup timing for each stm32 product: table 69. bootloader startup timings of stm32 devices device minimum bootloader startup (ms) hse timeout (ms) stm32f10xxx 1.227 n.a stm32f105xx/107xx pa9 pin low 1.396 n.a pa9 pin high 524.376 stm32f10xxx xl-density 1.227 n.a stm32l1xxx6(8/b) 0.542 n.a stm32l1xxxc 0.708 80 stm32l1xxxd 0.708 80 bootloader timing AN2606 142/155 docid13801 rev 21 stm32f2xxxx v2.x 134 n.a v3.x 84.59 0.790 stm32f40xxx/41xxx v3.x 84.59 0.790 v9.x 74 96 stm32f05xxx and stm32f030x8 devices 1.612 n.a stm32f03xxx 1.612 n.a stm32f373xx hse connected 43.4 2.236 hse not connected 2.36 stm32f302xb(c)/303xb(c) hse connected 43.4 2.236 hse not connected 2.36 stm32f378xx 1.542 n.a stm32f358xx 1.542 n.a stm32f429xx/439xx v7.x 82 97 v9.x 74 97 stm32f04xxx 0.058 n.a stm32f07xxx 0.058 n.a stm32f301xx/302x4(6/8) hse connected 45 560.5 hse not connected 560.8 stm32f318xx 0.182 n.a stm32f303x4(6/8)/334xx/328xx 0.155 n.a stm32f401xb(c) 74.5 85 stm32f401xd(e) 74.5 85 stm32f411xx 74.5 85 stm32f446xx tbd tbd stm32l1xxx6(8/b)a 0.542 n.a stm32l1xxxe 0.708 200 stm32l05xxx/06xxx 0.22 n.a stm32l476xx/486xx tbd tbd table 69. bootloader startup timings of stm32 devices (continued) device minimum bootloader startup (ms) hse timeout (ms) docid13801 rev 21 143/155 AN2606 bootloader timing 154 33.2 usart connection timing usart connection timing is the time that the host should wait for between sending the synchronization data (0x7f) and receiving the first acknowledge response (0x79). figure 41. usart connec tion timing description note: for stm32f105xx/107xx line devices, pa9 pi n (usb_vbus) is used to detect the usb host connection. the initialization of usb peripheral is performed only if pa9 is high at detection phase which means that a host is connected to the port and delivering 5 v on the usb bus. when pa9 level is high at detection phase, mo re time is required to initialize and shutdown the usb peripheral. to minimize bootloader dete ction time when pa9 pin is not used, keep pa9 state low during usart detection phase fr om the moment the de vice is reset till a device ack is sent. 0 6 9 }}?o} ? ? ?]}v ?]u ,}?? ? v? ? & ] ? v? < ?? ?? ] ? ] ? ? & ,}?? ? ] ? ?? ~ < }}?o} ? ? ? ?} ? ] v ? ? }uuv? ??]}v }( ?? ? v]vp ?z?}pz h ^ z d ~ ? v? }v ?? ??]}v }( h ^ z d ? ?]?z ?o }v(]p??]}v table 70. usart bootloader minimum timings of stm32 devices device one usart byte sending (ms) usart configuration (ms) usart connection (ms) stm32f10xxx 0.078125 0.002 0.15825 stm32f105xx/107xx pa9 pin low 0.078125 0.007 0.16325 pa9 pin high 105 105.15625 stm32f10xxx xl-density 0.078125 0.006 0.16225 stm32l1xxx6(8/b) 0 .078125 0. 008 0.16425 stm32l1xxxc 0.078 125 0.008 0.16425 stm32l1xxxd 0.078 125 0.008 0.16425 stm32f2xxxx v2.x 0.078125 0.009 0.16525 v3.x bootloader timing AN2606 144/155 docid13801 rev 21 33.3 usb connection timing usb connection timing is the time that the hos t should wait for between plugging the usb cable and establishing a correct connection with the device. this timing includes enumeration and dfu components configuratio n. usb connection depends on the host. stm32f40xxx/41xxx v3.x 0.078125 0.009 0.16525 v9.x 0.0035 0.15975 stm32f05xxx and stm32f030x8 devices 0.078125 0.0095 0.16575 stm32f03xxx 0.078125 0.0064 0.16265 stm32f373xx hse connected 0.078125 0.002 0.15825 hse not connected stm32f302xb(c)/303xb( c) hse connected 0.078125 0.002 0.15825 hse not connected stm32f378xx 0.15625 0.001 0.3135 stm32f358xx 0.15625 0.001 0.3135 stm32f429xx/439xx v7.x 0.078125 0.007 0.16325 v9.x 0.00326 0.15951 stm32f04xxx 0.078125 0.007 0.16325 stm32f07xxx 0.078125 0.007 0.16325 stm32f301xx/302x4(6/8) hse connected 0.078125 0.002 0.15825 hse not connected stm32f318xx 0.078125 0.002 0.15825 stm32f303x4(6/8)/334xx /328xx 0.078125 0.002 0.15825 stm32f401xb(c) 0.078125 0.00326 0.15951 stm32f401xd(e) 0.078125 0.00326 0.15951 stm32f411xx 0.078125 0.00326 0.15951 stm32f446xx tbd tbd tbd stm32l1xxx6(8/b)a 0.078125 0. 008 0.16425 stm32l1xxxe 0.078 125 0.008 0.16425 stm32l05xxx/06xxx 0. 078125 0.018 0.17425 stm32l476xx/486xx tbd tbd tbd table 70. usart bootloader minimum timings of stm32 devices (continued) device one usart byte sending (ms) usart configuration (ms) usart connection (ms) docid13801 rev 21 145/155 AN2606 bootloader timing 154 figure 42. usb connecti on timing description note: for stm32f105xx/107xx devices, if the exte rnal hse crystal frequency is different from 25 mhz (14.7456 mhz or 8 mhz), the device performs seve ral unsuccessful enumerations (with connect ? disconnect sequences) before being able to establish a correct connection with the host. this is due to the hse automa tic detection mechanism based on start of frame (sof) detection. 0 6 y 9 }}?o} ? ? ?]}v ?]u ] ? ? ? }}?o} ? ? ? ?} ???? ? ?]}v ?z? ??]}v }( }}?o} ? ? ?}? ? ]v]?]o]?]}v table 71. usb bootloader minimum timings of stm32 devices device usb connection (ms) stm32f105xx/107xx hse = 25 mhz 460 hse = 14.7465 mhz 4500 hse = 8 mhz 13700 stm32l1xxxc 849 stm32l1xxxd 849 stm32f2xxxx 270 stm32f40xxx/41xxx v3.x 270 v9.x 250 stm32f373xx 300 stm32f302xb(c)/303xb(c) 300 stm32f429xx/439xx v7.x 250 250 v9.x stm32f04xxx 350 stm32f07xxx 350 stm32f301xx/302x4(6/8) 300 stm32f401xb(c) 250 stm32f401xd(e) 250 stm32f411xx 250 bootloader timing AN2606 146/155 docid13801 rev 21 33.4 i2c connection timing i2c connection timing is the time that the ho st should wait for between sending i2c device address and sending command code. this timing includes i2c line stretching duration. figure 43. i2c connection timing description note: for i2c communication, a timeout mechanism is implemented and it must be respected to execute bootloader commands correctly. this timeout is implemented between two i2c frames in the same command (eg: for writ e memory command a timeout is inserted between command sending frame and address memory sending frame). also the same timeout period is inserted between two successi ve data reception or transmission in the same i2c frame. if the timeout period is el apsed a system reset is generated to avoid bootloader crash. in erase memory command and read-out unprotect command, the duration of flash operation should be taken into consideration when implementing the host side. after sending the code of pages to be erased, the host should wait until the bootloader device performs page erasing to complete the remaining steps of erase command. stm32f446xx tbd stm32l476xx/486xx tbd table 71. usb bootloader minimum ti mings of stm32 devices (continued) device usb connection (ms) 0 6 9 }}?o} ? ? ?]}v ?]u ,}?? ? v? ???? }v]?]}v = ] ? ?? ] lv}o p ? ]?? ? ?? v ??? ?z o]v }}?o} ? ? ? ?} ? ] v ? ? }uuv? ??]}v }( ???? = ?? ? v]vp ?z?}pz /? ~ ? v? }v }uu v]?]}v ?? ??]}v }( /? o]v ??? ?z]vp ,}?? ? ] ? lv}o p docid13801 rev 21 147/155 AN2606 bootloader timing 154 33.5 spi connection timing spi connection timing is the time that the host should wait for between sending the synchronization data (0xa5) and receiving the first acknowledge response (0x79). figure 44. spi connection timing description table 72. i2c bootloader minimu m timings of stm32 devices device start condition + one i2c byte sending (ms) i2c line stretching (ms) i2c connection (ms) i2c timeout (ms) stm32f40xxx/41xxx 0.02 25 0.0022 0.0247 1000 stm32f378xx 0.0225 0.0055 0.028 10 stm32f358xx 0.0225 0.0055 0.028 10 stm32f429xx/439xx v7.x 0.0225 0.0033 0.0258 1000 v9.x 0.0022 0.0247 stm32f04xxx 0.0225 0.0025 0.025 1000 stm32f07xxx 0.0225 0.0025 0.025 1000 stm32f318xx 0.0225 0.0027 0.0252 1000 stm32f303x4(6/8)/334xx/328xx 0.0225 0.0027 0.0252 1000 stm32f401xb(c) 0.0225 0022 0.0247 1000 stm32f401xd(e) 0.0225 0022 0.0247 1000 stm32f411xx 0.0225 0022 0.0247 1000 stm32f446xx tbd tbd tbd tbd stm32l476xx/486xx tbd tbd tbd tbd 0 6 9 }}?o} ? ? ?]}v ?]u ,}?? ? v? ?? ] ? v? < ?? ?? ] ? ] ? ?? ,}?? ? ] ? < ?? ?? }}?o} ? ? ? ?} ? ] v ? ? }uuv? ??]}v }( ?? ? v]vp ?z?}pz ^ w / ~ ? v? }v }uuv]?]} v ?? o? ? v ?} ?? ? bootloader timing AN2606 148/155 docid13801 rev 21 table 73. spi bootloader minimum timings of stm32 devices device one spi byte sending (ms) delay between two bytes(ms) spi connection (ms) all products 0.001 0.008 0.01 docid13801 rev 21 149/155 AN2606 revision history 154 34 revision history table 74. document revision history date revision changes 22-oct-2007 1 initial release. 22-jan-2008 2 all stm32 in production (rev. b and rev. z) include the bootloader described in this application note. modified: section 3.1: bootloader activation and section 1.4: bootloader code sequence . added: section 1.3: hardware requirements , section 1.5: choosing the usart baud rate , section 1.6: using the bootloader and section: note 2 linked to get, get version & read protection status and get id commands in table 3: bootloader commands , note 3 added. notion of ?permanent? (perma nent write unprotect/readout protect/unprotect) removed from document. small text changes. bootloader version upgraded to 2.0. 26-may-2008 3 small text changes. ram and system memory added to table : the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution . section 1.6: using the bootloader on page 8 removed. erase modified, note 3 modified and note 1 added in table 3: bootloader commands on page 9 . byte 3: on page 11 modified. byte 2: on page 13 modified. byte 2: , bytes 3-4: and byte 5: on page 15 modified, note 3 modified. byte 8: on page 18 modified. notes added to section 2.5: go command on page 18 . figure 11: go command: device side on page 20 modified. note added in section 2.6: write memory command on page 21 . byte 8: on page 24 modified. figure 14: erase memory command: host side and figure 15: erase memory command: device side modified. byte 3: on page 26 modified. table 3: bootloader commands on page 9 . note modified and note added in section 2.8: write protect command on page 27 . figure 16: write protect command: host side , figure 17: write protect command: device side , figure 19: write unprotect command: device side , figure 21: readout protect command: device side and figure 23: readout unprotect command: device side modified. 29-jan-2009 4 this application note also applies to the stm32f102xx microcontrollers. bootloader version updated to v2.2 (see table 4: bootloader versions ). revision history AN2606 150/155 docid13801 rev 21 19-nov-2009 5 iwdg added to table : the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution. . note added. bl changed bootloader in the entire document. go command description modified in table : the system clock is derived from the embedded internal high-speed rc, no external quartz is required for the bootloader execution . number of bytes awaited by the bootloader corrected in section 2.4: read memory command . note modified below figure 10: go command: host side . note removed in section 2.5: go command and note added. start ram address specified and note added in section 2.6: write memory command . all options are erased when a write memory command is issued to the option byte area. figure 11: go command: device side modified. figure 13: write memory command: device side modified. note added and bytes 3 and 4 sent by the host modified in section 2.7: erase memory command . note added to section 2.8: write protect command . 09-mar-2010 6 application note restructured. valu e line and connectivity line device bootloader added (replaces an2662). introduction changed. glossary added. 20-apr-2010 7 related documents : added xl-density line datasheets and programming manual. glossary : added xl-density line devices. table 3 : added information for xl-density line devices. section 4.1: bootloader configuration : updated first sentence. section 5.1: bootloader configuration : updated first sentence. added section 6: stm32f10xxx xl-density devices bootloader . table 65 : added information for xl-density line devices. 08-oct-2010 8 added information for high-density value line devices in table 3 and table 65 . 14-oct-2010 9 removed references to obsolete devices. 26-nov-2010 10 added information on ultralow power devices. 13-apr-2011 11 added information related to stm32f205/215xx and stm32f207/217xx devices. added section 32: bootloader timing 06-jun-2011 12 updated: ? table 12: stm32l1xxx6(8/b) bootloader versions ? table 17: stm32f2xxxx configuratio n in system memory boot mode ? table 18: stm32f2xxxx bootloader v2.x versions ? table 20: stm32f2xxxx bootloader v3.x versions 28-nov-2011 13 added information related to stm32f405/415xx and stm32f407/417xx bootloader, and stm32f105xx/107xx bootloader v2.1. added value line devices in section 4: stm32f10xxx devices bootloader title and overview. table 74. document revision history (continued) date revision changes docid13801 rev 21 151/155 AN2606 revision history 154 30-jul-2012 14 added information related to stm32f051x6/stm32f051x8 and to high- density ultralow power stm32l 151xx, stm32l152xx bootloader. added case of boot1 bit in section 3.1: bootloader activation . updated connectivity line, high-density ultralow power line, stm32f2xx and stm32f4xx in table 3: embedded bootloaders . added bootloader version v2.2 in table 8: stm32f105xx/107xx bootloader versions . added bootloader v2.2 in section 5.3.1: how to identify stm32f105xx/107xx bootloader versions . added note related to dfu interface below table 15: stm32l1xxxx high- density configuration in system memory boot mode . added v4.2 bootloader know limitations and updated description, and added v4.5 bootloader in table 16: stm32l1 xxxx high-density b ootloader versions . added note related to dfu interface below table 19: stm32f2xxxx configuration in system memory boot mode . added v3.2 bootloader know limitations, and added v3.3 bootloader in table 20: stm32f 2xxxx bootloader v3.x versions . updated stm32f2xx and stm32f4xx system memory end address in table 21: stm32f40xxx/ 41xxx configuration in system memory boot mode . added note related to dfu interface below table 21: stm32f40xxx/41xxx configuration in system memory boot mode . added v3.0 bootloader know limitations, and added v3.1 bootloader in table 22: stm32f40xxx/41xxx bootloader v3.x version . added bootloader v2.1 know limitations in table 26: stm32f051xx bootloader versions . updated stm32f051x6/x8 system memory end address in table 65: bootloader device-dependent parameters . added table 75: usart bootloader timings for high-density ultralow power devices , and table 78: usart bootloader timings for stm32f051xx devices . added table 88: usb minimum timings for high-density ultralow power devices . table 74. document revision history (continued) date revision changes revision history AN2606 152/155 docid13801 rev 21 24-jan-2013 15 updated generic product names throughout the document (see glossary ). added the following new sections: ? section 8: stm32l1xxxc devices bootloader . ? section 13: stm32f031xx devices bootloader . ? section 14: stm32f373xx devices bootloader . ? section 15: stm32f302xb(c)/3 03xb(c) devices bootloader . ? section 16: stm32f378xx devices bootloader . ? section 17: stm32f358xx devices bootloader . ? section 18: stm32f427xx/437xx devices bootloader . ? section 34.3: i2c bootloader timing characteristics . updated section 1: related documents and section 2: glossary . added table 79 to table 85 (usart bootloader timings). replaced figure 6 to figure 16 , and figures 18 , 19 and 42 . modified tables 3 , 5 , 9 , 11 , 17 , 20 , 21 , 22 to 13 , 27 , 29 , 31 , 33 , 35 , 37 and 65 . removed ?x = 6: one usart is used? in section 3.3: hardware connection requirement . replaced address 0x1ffff 8002 with address 0x1fff f802 in section 12.1: bootloader configuration . modified procedure related to exec ution of the bootloader code in note: on page 28 , in section 6.2: bootloader selection and in section 9.2: bootloader selection . 06-feb-2013 16 added information related to i 2 c throughout the document. streamlined table 1: applicable products and section 1: related documents . modified table 3: embedded bootloaders as follows: ? replaced "v6.0" with "v1.0" ? replaced "0x1ffff7a6" with "0x1ffff796" in row stm32f31xx ? replaced "0x1fff7fa6" with "0x1ffff7a6" in row stm32f051xx updated figures 6 , 9 and 11 . added note: in glossary and note: in section 3.1: bootloader activation . replaced: ? "1.62 v" with "1.8 v" in tables 17 , 19 , 19 , 22 , 21 , 27 , 37 and 59 ? "5 kbytes" with "4 kbytes" in row ram of table 33 ? "127 pages (2 kb each)" with "4 kb (2 pages of 2 kb each)" in rows f3 of table 65 ? "the bootloader id is pr ogrammed in the last two bytes of the device system memory" with "the bootloader id is pr ogrammed in the last byte address - 1 of the device system memory" in section 3.3: hardware connection requirement . ? "stm32f2xxxx devices revision y" by "stm32f2xxxx devices revision x and y" in section 10: stm32f2 xxxx devices bootloader ? ?voltage range 2? with ?voltage range 1? in tables 11 , 15 and 26 . table 74. document revision history (continued) date revision changes docid13801 rev 21 153/155 AN2606 revision history 154 21-may-2013 17 updated: ? introduction ? section 2: glossary ? section 3.3: hardware connection requirement ? section 7: stm32l1xxx6(8 /b) devices bootloader to include stm32l100 value line ? section 32.2: usart connection timing ? section 34.2: usb bootloader timing characteristics ? section 34.3: i2c bootloader timing characteristics ? table 1: applicable products ? table 3: embedded bootloaders ? table 25: stm32f051xx configurati on in system memory boot mode ? table 27: stm32f031xx configurati on in system memory boot mode ? table 65: bootloader device-dependent parameters ? figure 17: bootloader selection for stm32f031xx devices added section 19: stm32f429xx/439xx devices bootloader . 19-may-2014 18 add: ? figure 1 to figure 5 , figure 15 , figure 17 , figure 18 , figure 20 , figure 21 , from figure 24 to figure 40 , figure 44 ? table 4 , table 24 , table 25 , from table 28 to table 31 , from table 34 to table 37 , from table 40 to table 41 , from table to table 73 ? section 11.2 , section 18.2 , section 33.1 , section 33.5 ? section 13 , section 14 , section 16 , section 17 , from section 19 to section 29 ? note under figure 1 , figure 2 , figure 3 and figure 4 updated: ? updated starting from section 3 to section 12 and section 15 , section 18 and section 18 the chapter structure org anized in three subsection: bootloader configuration, bootloader selection and bootloader version. updated section 30 and section 33 ? updated block diagram of figure 18 and figure 19 . ? fixed i2c address for stm32f429xx/439xx devices in table 38 ? table 1 , table 2 , table 3 , table 8 , table 12 , table 14 , table 16 , table 18 , table 20 , table 22 , table 68 ?from figure 6 , to figure 14 , figure 16 , from figure 40 to figure 44 ? note on table 13 table 74. document revision history (continued) date revision changes revision history AN2606 154/155 docid13801 rev 21 29-jul-2014 19 updated: ? notes under ta ble 2 ? figure 11 and figure 35 ? section 2: glossary ? replaced any reference to stm32f 427xx/437xx with stm32f42xxx/43xxx on section 18: stm32f42xxx/ 43xxx devices bootloader ? replace any occurrence of ?s tm32f072xx? with ?stm32f07xxx? ? replace any occurrence of ?stm32f051xx? with ?stm32f051xx and stm32f030x8 devices?. ? comment field related to otg_fs_dp and otg_fs_dm on table 8 , table 20 , table 22 , table 24 , table 38 , table 40 , table 42 , table 44 , table 52 , table 54 and table 56 ? comment field related to usb_dm on table 60 . ? replace reference to "stm32f429xx/439xx" by "stm32f42xxx/43xxx? on table 3 ? comment field related to spi2_mosi, spi2_miso, spi2_sck and spi2_nss pins on table 40 added: ? note under ta ble 2 ? reference to stm32f411 on table 1 , section 2: glossary , table 69 , table 70 , table 71 , table 72 ? section 26: stm32f41 1xx devices bootloader removed reference to stm32f427xx/437xx on table 3 , section 2: glossary , table 68 , table 69 , table 70 , table 71 24-nov-2014 20 updated: ? comment in ?spi1_nss pin" and "spi2_nss pin" rows on table 24 and table 62 ? comment in "spi1_nss pin", "spi2_nss pin" and "spi3_nss pin" rows on table 52 , table 54 and table 56 ? figure 1 11-mar-2015 21 updated: ? table 1 , table 3 , table 6 , table 10 , table 12 , table 18 , table 20 , table 21 , table 22 , table 24 , table 26 , table 27 , table 28 , table 32 , table 38 , table 40 , table 42 , table 43 , table 44 , table 45 , table 46 , table 58 , table 64 , table 68 , table 69 , table 70 , table 71 and table 72 ? figure 38 ? chapter 2: glossary ? section 3.1 and section 3.4 added: ? section 30: stm32l476xx/486xx devices bootloader and section 31: stm32f446xx devices bootloader table 74. document revision history (continued) date revision changes docid13801 rev 21 155/155 AN2606 155 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 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